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Research Output 1983 2019

2019

Acceleration of deep recurrent neural networks with an FPGA cluster

Sun, Y., Ben Ahmed, A. & Amano, H., 2019 Jun 6, Proceedings of the 10th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, HEART 2019. Association for Computing Machinery, 18. (ACM International Conference Proceeding Series).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Recurrent neural networks
Computer hardware
Program processors
Field programmable gate arrays (FPGA)
Hardware

A coarse grained-reconfigurable accelerator with energy efficient MTJ-based non-volatile flip-flops

Ikezoe, T., Amano, H., Akaike, J., Usami, K., Kudo, M., Hiraga, K., Shuto, Y. & Yagami, K., 2019 Feb 13, 2018 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2018. Andrews, D., Feregrino, C., Cumplido, R. & Stroobandt, D. (eds.). Institute of Electrical and Electronics Engineers Inc., 8641712. (2018 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2018).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Flip flop circuits
Particle accelerators
Data storage equipment
Managers
Inventory control

A fine-grained multicasting of configuration data for coarse-grained reconfigurable architectures

Kojima, T. & Amano, H., 2019 Jan 1, In : IEICE Transactions on Information and Systems. E102D, 7, p. 1247-1256 10 p.

Research output: Contribution to journalArticle

Open Access
Reconfigurable architectures
Multicasting
Processing
Program processors
Energy utilization

An ARM-based heterogeneous FPGA accelerator for hall thruster simulation

Noda, H., Orsztynowicz, M., Iizuka, K., Miyajima, T., Fujita, N. & Amano, H., 2019 Jun 6, Proceedings of the 10th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, HEART 2019. Association for Computing Machinery, 9. (ACM International Conference Proceeding Series).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

ARM processors
Hall thrusters
Digital arithmetic
Space research
Random access storage

Implementing a large application(LSTM) on the multi-FPGA system: Flow-in-Cloud

Yamauchi, Y., Musha, K. & Amano, H., 2019 May 23, IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2019 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 8721333. (IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2019 - Proceedings).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Field programmable gate arrays (FPGA)
Cloud computing
Long short-term memory
Engines
Tensors

Key-value Store Chip Design for Low Power Consumption

Tokusashi, Y., Matsutani, H. & Amano, H., 2019 May 23, IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2019 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 8721352. (IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2019 - Proceedings).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Electric power utilization
Bias voltage
Tuning
Application programming interfaces (API)
Embedded systems

Level-Shifter-Less Approach for Multi-VDD SoC Design to Employ Body Bias Control in FD-SOI

Usami, K., Kogure, S., Yoshida, Y., Magasaki, R. & Amano, H., 2019 Jan 1, VLSI-SoC: Opportunities and Challenges Beyond the Internet of Things - 25th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017, Revised and Extended Selected Papers. Monteiro, J., Elfadel, I. A. M., Sonza Reorda, M., Ugurdag, H. F., Maniatakos, M. & Reis, R. (eds.). Springer New York LLC, p. 1-21 21 p. (IFIP Advances in Information and Communication Technology; vol. 500).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Simulation
Costs
Temperature

Sparse 3-D NoCs with inductive coupling

Koibuchi, M., Leong, L., Totoki, T., Niwa, N., Matsutani, H., Amano, H. & Casanova, H., 2019 Jun 2, Proceedings of the 56th Annual Design Automation Conference 2019, DAC 2019. Institute of Electrical and Electronics Engineers Inc., a49. (Proceedings - Design Automation Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3D
Layout
Chip
Network Topology
Topology

The evaluation of partial reconfiguration for a multi-board FPGA system FiCSW

Yamakura, M., Hironaka, K., Azegami, K., Musha, K. & Amano, H., 2019 Jun 6, Proceedings of the 10th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, HEART 2019. Association for Computing Machinery, 15. (ACM International Conference Proceeding Series).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Field programmable gate arrays (FPGA)
Integrated circuit design
Switches
Bandwidth
Networks (circuits)
2018
1 Citation (Scopus)

A configuration data multicasting method for coarse-grained reconfigurable architectures

Kojima, T. & Amano, H., 2018 Nov 9, Proceedings - 2018 International Conference on Field-Programmable Logic and Applications, FPL 2018. Institute of Electrical and Electronics Engineers Inc., p. 239-242 4 p. 8533501. (Proceedings - 2018 International Conference on Field-Programmable Logic and Applications, FPL 2018).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Reconfigurable architectures
Multicasting
Processing
Data compression
Scheduling algorithms

Adaptive body bias control scheme for ultra low-power network-on-chip systems

Ben Ahmed, A., Okuhara, H., Matsutani, H., Koibuchi, M. & Amano, H., 2018 Nov 16, Proceedings - 2018 IEEE 12th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2018. Institute of Electrical and Electronics Engineers Inc., p. 146-153 8 p. 8540227

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Routers
Bias voltage
Pipelines
Silicon on insulator technology
Leakage (fluid)

Analysis of body bias control using overhead conditions for real time systems: A practical approach

Torres, C. C. C., Okuhara, H., Yamasaki, N. & Amano, H., 2018 Apr 1, In : IEICE Transactions on Information and Systems. E101D, 4, p. 1116-1125 10 p.

Research output: Contribution to journalArticle

Real time systems
Embedded systems
Energy efficiency
Silicon

An extension of a temperature modeling tool hotspot 6.0 for castle-of-chips stacking

Totoki, T., Koibuchi, M. & Amano, H., 2018 Dec 26, Proceedings - 2018 6th International Symposium on Computing and Networking Workshops, CANDARW 2018. Institute of Electrical and Electronics Engineers Inc., p. 363-369 7 p. 8590927. (Proceedings - 2018 6th International Symposium on Computing and Networking Workshops, CANDARW 2018).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Stacking
Hot Spot
Chip
Cooling
Heat sinks

An inductive-coupling link for 3-D Network-on-Chips

Kadomoto, J., Amano, H. & Kuroda, T., 2018 May 29, Proceedings - International SoC Design Conference 2017, ISOCC 2017. Institute of Electrical and Electronics Engineers Inc., p. 150-151 2 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Silicon
Transceivers
Networks (circuits)
Communication
Network-on-chip

An trace-driven performance prediction method for exploring noc design optimization

Niwa, N., Totoki, T., Matsutani, H., Koibuchi, M. & Amano, H., 2018 Dec 26, Proceedings - 2018 6th International Symposium on Computing and Networking Workshops, CANDARW 2018. Institute of Electrical and Electronics Engineers Inc., p. 182-185 4 p. 8590896. (Proceedings - 2018 6th International Symposium on Computing and Networking Workshops, CANDARW 2018).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Performance Prediction
Trace
System Simulation
Cycle
Execution Time

A Practical Collision Avoidance Method for an Inter-Chip Bus with Wireless Inductive through Chip Interface

Nomura, A., Kadomoto, JI., Kuroda, T. & Amano, H., 2018 Apr 23, Proceedings - 2017 5th International Symposium on Computing and Networking, CANDAR 2017. Institute of Electrical and Electronics Engineers Inc., Vol. 2018-January. p. 126-131 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Collision avoidance
Carrier sense multiple access
Throughput
2 Citations (Scopus)

Asymmetric Body Bias Control With Low-Power FD-SOI Technologies: Modeling and Power Optimization

Okuhara, H., Ben Ahmed, A., Kuhn, J. M. & Amano, H., 2018 Mar 23, (Accepted/In press) In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Research output: Contribution to journalArticle

Power control
Silicon on insulator technology
Testing
Electric potential
Microcontrollers

AxNoC: Low-power Approximate Network-on-Chips using Critical-Path Isolation

Ahmed, A. B., Fujiki, D., Matsutani, H., Koibuchi, M. & Amano, H., 2018 Oct 26, 2018 12th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2018. Institute of Electrical and Electronics Engineers Inc., 8512158

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Electric potential
Routers
Electric power utilization
Data transfer
Network-on-chip

Body Bias Control for Renewable Energy Source with a High Inner Resistance

Azegami, K., Okuhara, H. & Amano, H., 2018 Apr 16, (Accepted/In press) In : IEEE Transactions on Multi-Scale Computing Systems.

Research output: Contribution to journalArticle

Stars
Solar cells
Bias voltage
Sensor nodes
Leakage currents
1 Citation (Scopus)

Break even time analysis using empirical overhead parameters for embedded systems on SOTB technology

Cortes, C., Amano, H. & Yamasaki, N., 2018 Mar 9, 2017 32nd Conference on Design of Circuits and Integrated Systems, DCIS 2017 - Proceedings. Institute of Electrical and Electronics Engineers Inc., Vol. 2017-November. p. 1-6 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Embedded systems
Energy conservation
Silicon
Microcontrollers
Internet of things

Building block multi-chip systems using inductive coupling through chip interface

Amano, H., Kuroda, T., Nakamura, H., Usami, K., Kondo, M., Matsutani, H. & Namiki, M., 2018 May 29, Proceedings - International SoC Design Conference 2017, ISOCC 2017. Institute of Electrical and Electronics Engineers Inc., p. 152-154 3 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Computer operating systems
Network architecture
Interfaces (computer)
Networks (circuits)
Hot Temperature

Building block operating system for 3D stacked computer systems with inductive coupling interconnect

Hamada, S., Koshiba, A., Namiki, M. & Amano, H., 2018 May 29, Proceedings - International SoC Design Conference 2017, ISOCC 2017. Institute of Electrical and Electronics Engineers Inc., p. 157-158 2 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Computer operating systems
Computer systems
Silicon
Particle accelerators

C4: An FPGA-based compression algorithm for expether

Shimura, H., Noda, H. & Amano, H., 2018 Dec 26, Proceedings - 2018 6th International Symposium on Computing and Networking Workshops, CANDARW 2018. Institute of Electrical and Electronics Engineers Inc., p. 356-362 7 p. 8590926. (Proceedings - 2018 6th International Symposium on Computing and Networking Workshops, CANDARW 2018).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Ethernet
Data compression
Data Compression
Field Programmable Gate Array
Field programmable gate arrays (FPGA)
1 Citation (Scopus)

Deep learning on high performance FPGA switching boards: Flow-in-cloud

Musha, K., Kudoh, T. & Amano, H., 2018 Jan 1, Applied Reconfigurable Computing: Architectures, Tools, and Applications - 14th International Symposium, ARC 2018, Proceedings. Springer Verlag, p. 43-54 12 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 10824 LNCS).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Field Programmable Gate Array
Field programmable gate arrays (FPGA)
High Performance
Data Broadcasting
Circuit Switching

Design automation methodology of a critical path monitor for adaptive voltage controls

Kazami, R., Okuhara, H. & Amano, H., 2018 Jun 5, 21st IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL Chips 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc., p. 1-3 3 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Voltage control
Automation
Silicon
Electric potential
Bias voltage

Designing High-Performance Interconnection Networks with Host-Switch Graphs

Yasudo, R., Koibuchi, M., Nakano, K., Matsutani, H. & Amano, H., 2018 Aug 6, (Accepted/In press) In : IEEE Transactions on Parallel and Distributed Systems.

Research output: Contribution to journalArticle

Switches
Topology
Distributed computer systems
Network performance
Oils and fats
1 Citation (Scopus)

Digital embedded memory scheme using voltage scaling and body bias separation for low-power system

Yoshida, Y., Usami, K. & Amano, H., 2018 May 29, Proceedings - International SoC Design Conference 2017, ISOCC 2017. Institute of Electrical and Electronics Engineers Inc., p. 148-149 2 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Data storage equipment
Macros
Computer peripheral equipment
Flip flop circuits
Static random access storage

Digitally Assisted On-Chip Body Bias Tuning Scheme for Ultra Low-Power VLSI Systems

Okuhara, H., Ben Ahmed, A. & Amano, H., 2018 Mar 13, (Accepted/In press) In : IEEE Transactions on Circuits and Systems I: Regular Papers.

Research output: Contribution to journalArticle

Tuning
Electric potential
Silicon on insulator technology
Analog circuits
Bias voltage

Energy Efficient Write Verify and Retry Scheme for MTJ Based Flip-Flop and Application

Usami, K., Akaike, J., Akiba, S., Kudo, M., Amano, H., Ikezoe, T., Hiraga, K., Shuto, Y. & Yagami, K., 2018 Nov 15, Proceedings - 7th IEEE Non-Volatile Memory Systems and Applications Symposium, NVMSA 2018. Institute of Electrical and Electronics Engineers Inc., p. 91-98 8 p. 8537701

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Flip flop circuits
Sequential circuits
Energy dissipation
Durability
Image processing
2 Citations (Scopus)

FPGA-based accelerator for losslessly quantized convolutional neural networks

Sit, M., Kazami, R. & Amano, H., 2018 Feb 2, 2017 International Conference on Field-Programmable Technology, ICFPT 2017. Institute of Electrical and Electronics Engineers Inc., Vol. 2018-January. p. 295-298 4 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Particle accelerators
Field programmable gate arrays (FPGA)
accelerators
Neural networks
Computer vision

FPGA Design for Autonomous Vehicle Driving Using Binarized Neural Networks

Wei, K., Honda, K. & Amano, H., 2018 Dec 1, Proceedings - 2018 International Conference on Field-Programmable Technology, FPT 2018. Institute of Electrical and Electronics Engineers Inc., p. 428-431 4 p. 8742321. (Proceedings - 2018 International Conference on Field-Programmable Technology, FPT 2018).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Field programmable gate arrays (FPGA)
Neural networks
Edge detection
Embedded systems
Telecommunication traffic
2 Citations (Scopus)

Glitch-aware variable pipeline optimization for CGRAs

Kojima, T., Ando, N., Okuhara, H. & Amano, H., 2018 Feb 2, 2017 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2017. Institute of Electrical and Electronics Engineers Inc., Vol. 2018-January. p. 1-6 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Pipelines
Energy utilization
Processing
Energy efficiency

GPU-accelerated language and communication support by FPGA

Boku, T., Hanawa, T., Murai, H., Nakao, M., Miki, Y., Amano, H. & Umemura, M., 2018 Dec 6, Advanced Software Technologies for Post-Peta Scale Computing: The Japanese Post-Peta CREST Research Project. Springer Singapore, p. 301-317 17 p.

Research output: Chapter in Book/Report/Conference proceedingChapter

Field programmable gate arrays (FPGA)
Communication
Program processors
Hardware
Graphics processing unit
1 Citation (Scopus)

HiRy: An advanced theory on design of deadlock-free adaptive routing for arbitrary topologies

Kawano, R., Yasudo, R., Matsutani, H., Koibuchi, M. & Amano, H., 2018 May 29, Proceedings - 2017 IEEE 23rd International Conference on Parallel and Distributed Systems, ICPADS 2017. IEEE Computer Society, Vol. 2017-December. p. 664-673 10 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Topology
Routing algorithms
Network performance
Throughput

K-Optimized Path Routing for High-Throughput Data Center Networks

Kawano, R., Yasudo, R., Matsutani, H. & Amano, H., 2018 Dec 27, Proceedings - 2018 6th International Symposium on Computing and Networking, CANDAR 2018. Institute of Electrical and Electronics Engineers Inc., p. 99-105 7 p. 8594749. (Proceedings - 2018 6th International Symposium on Computing and Networking, CANDAR 2018).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Throughput
Warehouses
Switches
Bandwidth
1 Citation (Scopus)

Level-shifter free approach for multi-Vdd SOTB employing adaptive Vt modulation for pMOSFET

Usami, K., Kogure, S., Yoshida, Y., Magasaki, R. & Amano, H., 2018 Mar 7, 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017. Institute of Electrical and Electronics Engineers Inc., Vol. 2018-March. p. 1-3 3 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Modulation
Silicon
Electric potential
Threshold voltage
Microprocessor chips
1 Citation (Scopus)

Multi-objective optimization for application mapping and body bias control on a CGRA

Doan, N. A. V., Matsushita, Y., Ando, N., Okuhara, H. & Amano, H., 2018 Mar 26, Proceedings - IEEE 11th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2017. Institute of Electrical and Electronics Engineers Inc., Vol. 2018-January. p. 143-150 8 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Multiobjective optimization
Silicon
Bias voltage
Threshold voltage
Linear programming
1 Citation (Scopus)

Optimization of body biasing for variable pipelined coarse-grained reconfigurable architectures

Kojima, T., Ando, N., Okuhara, H., Doan, N. A. V. & Amano, H., 2018 Jun 1, In : IEICE Transactions on Information and Systems. E101D, 6, p. 1532-1540 9 p.

Research output: Contribution to journalArticle

Reconfigurable architectures
Pipelines
Bias voltage
Silicon
Energy utilization

Performance Estimation for Exascale Reconfigurable Dataflow Platforms

Yasudo, R., Coutinho, J., Varbanescu, A., Luk, W., Amano, H. & Becker, T., 2018 Dec 1, Proceedings - 2018 International Conference on Field-Programmable Technology, FPT 2018. Institute of Electrical and Electronics Engineers Inc., p. 317-320 4 p. 8742283. (Proceedings - 2018 International Conference on Field-Programmable Technology, FPT 2018).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Particle accelerators
Analytical models
Calibration

Performance Prediction for Large-Scale Heterogeneous Platforms

Yasudo, R., Varbanescu, A. L., Coutinho, J. G. F., Luk, W. & Amano, H., 2018 Sep 7, Proceedings - 26th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2018. Institute of Electrical and Electronics Engineers Inc., 1 p. 8457669

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Statistical Models

Proxy responses by FPGA-based switch for MapReduce stragglers

Mitsuzuka, K., Koibuchi, M., Amano, H. & Matsutani, H., 2018 Sep 1, In : IEICE Transactions on Information and Systems. E101D, 9, p. 2258-2268 11 p.

Research output: Contribution to journalArticle

Field programmable gate arrays (FPGA)
Switches
Ethernet
Communication
Processing

Real chip evaluation of a low power CGRA with optimized application mapping

Kojima, T., Ando, N., Matshushita, Y., Okuhara, H., Doan, N. A. V. & Amano, H., 2018 Jun 20, Proceedings of the 9th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, HEART 2018. Association for Computing Machinery, a13

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Reconfigurable architectures
Electric power utilization
Pipelines
Throughput
1 Citation (Scopus)

Scalable deep neural network accelerator cores with cubic integration using through chip interface

Sakamoto, R., Takata, R., Ishii, J., Kondo, M., Nakamura, H., Ohkubo, T., Kojima, T. & Amano, H., 2018 May 29, Proceedings - International SoC Design Conference 2017, ISOCC 2017. Institute of Electrical and Electronics Engineers Inc., p. 155-156 2 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Particle accelerators
Embedded systems
Interfaces (computer)
Scalability
Engines
1 Citation (Scopus)

Superpixel accelerator for computer vision applications on arria 10 SoC

Akagic, A., Buza, E., Turcinhodzic, R., Haseljic, H., Hiroyuki, N. & Amano, H., 2018 Jul 11, Proceedings - 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2018. Institute of Electrical and Electronics Engineers Inc., p. 55-60 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Image segmentation
Computer vision
Particle accelerators
Hardware
System-on-chip

The design and implementation of scalable deep neural network accelerator cores

Sakamoto, R., Takata, R., Ishii, J., Kondo, M., Nakamura, H., Ohkubo, T., Kojima, T. & Amano, H., 2018 Mar 26, Proceedings - IEEE 11th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2017. Institute of Electrical and Electronics Engineers Inc., Vol. 2018-January. p. 13-20 8 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Particle accelerators
Bandwidth
Data storage equipment
Embedded systems
Interfaces (computer)

Towards an optimized multi FPGA architecture with STDM network: A preliminary study

Hironaka, K., Doan, N. A. V. & Amano, H., 2018 Jan 1, Applied Reconfigurable Computing: Architectures, Tools, and Applications - 14th International Symposium, ARC 2018, Proceedings. Springer Verlag, p. 142-150 9 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 10824 LNCS).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Field Programmable Gate Array
Field programmable gate arrays (FPGA)
Communication
Multi-criteria
Energy Efficiency
2017

3D layout of spidergon, flattened butterfly and dragonfly on a chip stack with inductive coupling through chip interface

Nakahara, H., Yasudo, R., Matsutani, H., Amano, H. & Koibuchi, M., 2017 Nov 27, Proceedings - 14th International Symposium on Pervasive Systems, Algorithms and Networks, I-SPAN 2017, 11th International Conference on Frontier of Computer Science and Technology, FCST 2017 and 3rd International Symposium of Creative Computing, ISCC 2017. Institute of Electrical and Electronics Engineers Inc., Vol. 2017-November. p. 52-59 8 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Wire
Data transfer
Network-on-chip
1 Citation (Scopus)

A Case for Uni-directional Network Topologies in Large-Scale Clusters

Koibuchi, M., Totoki, T., Matsutani, H., Amano, H., Chaix, F., Fujiwara, I. & Casanova, H., 2017 Sep 22, Proceedings - 2017 IEEE International Conference on Cluster Computing, CLUSTER 2017. Institute of Electrical and Electronics Engineers Inc., Vol. 2017-September. p. 178-187 10 p. 8048929

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Topology
Switches
Flow control
Electric power utilization
Experiments
1 Citation (Scopus)

Acceleration of the aggregation process in a Hall-thruster simulation using Intel FPGA SDK for OpenCL

Noda, H., Sakai, R., Miyajima, T., Fujita, N. & Amano, H., 2017 Jun 7, Proceedings of the 8th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, HEART 2017. Association for Computing Machinery, 20

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Hall thrusters
Field programmable gate arrays (FPGA)
Agglomeration
Electric propulsion
Software packages