• 2613 Citations
  • 23 h-Index
1983 …2020

Research output per year

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Research Output

2020

Accelerating Deep Learning using Multiple GPUs and FPGA-Based 10GbE Switch

Itsubo, T., Koibuchi, M., Amano, H. & Matsutani, H., 2020 Mar, Proceedings - 2020 28th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2020. Institute of Electrical and Electronics Engineers Inc., p. 102-109 8 p. 9092145. (Proceedings - 2020 28th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2020).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A generalized theory based on the turn model for deadlock-free irregular networks

Kawano, R., Yasudo, R., Matsutani, H., Koibuchi, M. & Amano, H., 2020, In : IEICE Transactions on Information and Systems. E103D, 1, p. 101-110 10 p.

Research output: Contribution to journalArticle

Open Access

Body bias optimization for real-time systems

Torres, C. C. C., Yasudo, R. & Amano, H., 2020 Mar, In : Journal of Low Power Electronics and Applications. 10, 1, 8.

Research output: Contribution to journalArticle

Open Access

Implementation of FM-Index Based Pattern Search on a Multi-FPGA System

Ullah, M. M. I., Ben Ahmed, A. & Amano, H., 2020, Applied Reconfigurable Computing. Architectures, Tools, and Applications - 16th International Symposium, ARC 2020, Proceedings. Rincón, F., Barba, J., Caba, J., So, H. K. H. & Diniz, P. (eds.). Springer, p. 376-391 16 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 12083 LNCS).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Non-Volatile Coarse Grained Reconfigurable Array Enabling Two-step Store Control for Energy Minimization

Usami, K., Akiba, S., Amano, H., Ikezoe, T., Hiraga, K., Suzuki, K. & Kanda, Y., 2020 Apr, IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2020 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 9097630. (IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2020 - Proceedings).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2019

Acceleration of ART Algorithm on an FPGA Board with Xilinx SDAccel

Okamoto, Y. & Amano, H., 2019 Nov, Proceedings - 2019 7th International Symposium on Computing and Networking Workshops, CANDARW 2019. Institute of Electrical and Electronics Engineers Inc., p. 280-284 5 p. 8951517. (Proceedings - 2019 7th International Symposium on Computing and Networking Workshops, CANDARW 2019).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Acceleration of deep recurrent neural networks with an FPGA cluster

Sun, Y., Ben Ahmed, A. & Amano, H., 2019 Jun 6, Proceedings of the 10th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, HEART 2019. Association for Computing Machinery, 18. (ACM International Conference Proceeding Series).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

A coarse grained-reconfigurable accelerator with energy efficient MTJ-based non-volatile flip-flops

Ikezoe, T., Amano, H., Akaike, J., Usami, K., Kudo, M., Hiraga, K., Shuto, Y. & Yagami, K., 2019 Feb 13, 2018 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2018. Andrews, D., Feregrino, C., Cumplido, R. & Stroobandt, D. (eds.). Institute of Electrical and Electronics Engineers Inc., 8641712. (2018 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2018).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

A coarse-grained reconfigurable architecture with a fault tolerant non-volatile configurable memory

Ikezoe, T., Kojima, T. & Amano, H., 2019 Dec, Proceedings - 2019 International Conference on Field-Programmable Technology, ICFPT 2019. Institute of Electrical and Electronics Engineers Inc., p. 81-89 9 p. 8977850. (Proceedings - 2019 International Conference on Field-Programmable Technology, ICFPT 2019; vol. 2019-December).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A fine-grained multicasting of configuration data for coarse-grained reconfigurable architectures

Kojima, T. & Amano, H., 2019 Jan 1, In : IEICE Transactions on Information and Systems. E102D, 7, p. 1247-1256 10 p.

Research output: Contribution to journalArticle

Open Access

An ARM-based heterogeneous FPGA accelerator for hall thruster simulation

Noda, H., Orsztynowicz, M., Iizuka, K., Miyajima, T., Fujita, N. & Amano, H., 2019 Jun 6, Proceedings of the 10th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, HEART 2019. Association for Computing Machinery, 9. (ACM International Conference Proceeding Series).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A Preliminary evaluation of building block computing systems

Terashima, S., Kojima, T., Okuhara, H., Musha, K., Amano, H., Sakamoto, R., Kondo, M. & Namiki, M., 2019 Oct, Proceedings - 2019 IEEE 13th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019. Institute of Electrical and Electronics Engineers Inc., p. 312-319 8 p. 8906777. (Proceedings - 2019 IEEE 13th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A rapid optimization method for visual indirect SLAM using a subset of feature points

Kazami, R. & Amano, H., 2019 Nov, Proceedings - 2019 7th International Symposium on Computing and Networking Workshops, CANDARW 2019. Institute of Electrical and Electronics Engineers Inc., p. 275-279 5 p. 8951546. (Proceedings - 2019 7th International Symposium on Computing and Networking Workshops, CANDARW 2019).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A Stdm (static time division multiplexing) switch on a multi-fpga system

Azegami, K., Musha, K., Hironaka, K., Ben Ahmed, A., Koibuch, M., Hu, Y. & Amano, H., 2019 Oct, Proceedings - 2019 IEEE 13th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019. Institute of Electrical and Electronics Engineers Inc., p. 328-333 6 p. 8906518. (Proceedings - 2019 IEEE 13th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A System delay monitor exploiting automatic cell-based design flow and post-silicon calibration

Okuhara, H., Kazami, R. & Amano, H., 2019 Oct, Proceedings - 2019 IEEE 13th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019. Institute of Electrical and Electronics Engineers Inc., p. 32-37 6 p. 8906740. (Proceedings - 2019 IEEE 13th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Deadlock-free layered routing for infiniband networks

Kawano, R., Matsutani, H. & Amano, H., 2019 Nov, Proceedings - 2019 7th International Symposium on Computing and Networking Workshops, CANDARW 2019. Institute of Electrical and Electronics Engineers Inc., p. 84-90 7 p. 8951557. (Proceedings - 2019 7th International Symposium on Computing and Networking Workshops, CANDARW 2019).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Demonstration of flow-in-cloud: A multi-FPGA system

Hironaka, K., Iizuka, K., Ben Ahmed, A., Imdad Ullah, M. M., Yamauchi, Y., Sun, Y., Yamakura, M., Hiruma, A. & Amano, H., 2019 Sep, Proceedings - 29th International Conference on Field-Programmable Logic and Applications, FPL 2019. Sourdis, I., Bouganis, C-S., Alvarez, C., Toledo Diaz, L. A., Valero, P. & Martorell, X. (eds.). Institute of Electrical and Electronics Engineers Inc., p. 417-418 2 p. 8892139. (Proceedings - 29th International Conference on Field-Programmable Logic and Applications, FPL 2019).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Demonstration of low power stream processing using a variable pipelined CGRA

Kojima, T., Ando, N., Matsushita, Y. & Amano, H., 2019 Sep, Proceedings - 29th International Conference on Field-Programmable Logic and Applications, FPL 2019. Sourdis, I., Bouganis, C-S., Alvarez, C., Toledo Diaz, L. A., Valero, P. & Martorell, X. (eds.). Institute of Electrical and Electronics Engineers Inc., p. 411-412 2 p. 8892240. (Proceedings - 29th International Conference on Field-Programmable Logic and Applications, FPL 2019).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Fpga/python co-design for lane line detection on a pynq-z1 board

Honda, K., Wei, K. & Amano, H., 2019 Oct, Proceedings - 2019 IEEE 13th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019. Institute of Electrical and Electronics Engineers Inc., p. 53-60 8 p. 8906682. (Proceedings - 2019 IEEE 13th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Implementing a large application(LSTM) on the multi-FPGA system: Flow-in-Cloud

Yamauchi, Y., Musha, K. & Amano, H., 2019 May 23, IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2019 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 8721333. (IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2019 - Proceedings).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Key-value Store Chip Design for Low Power Consumption

Tokusashi, Y., Matsutani, H. & Amano, H., 2019 May 23, IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2019 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 8721352. (IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2019 - Proceedings).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Level-Shifter-Less Approach for Multi-VDD SoC Design to Employ Body Bias Control in FD-SOI

Usami, K., Kogure, S., Yoshida, Y., Magasaki, R. & Amano, H., 2019 Jan 1, VLSI-SoC: Opportunities and Challenges Beyond the Internet of Things - 25th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017, Revised and Extended Selected Papers. Monteiro, J., Elfadel, I. A. M., Sonza Reorda, M., Ugurdag, H. F., Maniatakos, M. & Reis, R. (eds.). Springer New York LLC, p. 1-21 21 p. (IFIP Advances in Information and Communication Technology; vol. 500).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Multi-FPGA Management on Flow-in-Cloud Prototype System

Hironaka, K., Akram, B. A. & Amano, H., 2019 Jul, Proceedings - 20th IEEE/ACIS International Conference on Software Engineering, Artificial Intelligence, Networking and Parallel/Distributed Computing, SNPD 2019. Nakamura, M., Hirata, H., Ito, T., Otsuka, T. & Okuhara, S. (eds.). Institute of Electrical and Electronics Engineers Inc., p. 443-448 6 p. 8935738. (Proceedings - 20th IEEE/ACIS International Conference on Software Engineering, Artificial Intelligence, Networking and Parallel/Distributed Computing, SNPD 2019).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Real chip performance evaluation on through chip interface IP for renesas SOTB 65nm process

Kayashima, H., Kojima, T., Okuhara, H., Shidei, T. & Amano, H., 2019 Nov, Proceedings - 2019 7th International Symposium on Computing and Networking Workshops, CANDARW 2019. Institute of Electrical and Electronics Engineers Inc., p. 269-274 6 p. 8951550. (Proceedings - 2019 7th International Symposium on Computing and Networking Workshops, CANDARW 2019).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Sparse 3-D NoCs with inductive coupling

Koibuchi, M., Leong, L., Totoki, T., Niwa, N., Matsutani, H., Amano, H. & Casanova, H., 2019 Jun 2, Proceedings of the 56th Annual Design Automation Conference 2019, DAC 2019. Institute of Electrical and Electronics Engineers Inc., a49. (Proceedings - Design Automation Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

The evaluation of partial reconfiguration for a multi-board FPGA system FiCSW

Yamakura, M., Hironaka, K., Azegami, K., Musha, K. & Amano, H., 2019 Jun 6, Proceedings of the 10th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, HEART 2019. Association for Computing Machinery, 15. (ACM International Conference Proceeding Series).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)
2018

A configuration data multicasting method for coarse-grained reconfigurable architectures

Kojima, T. & Amano, H., 2018 Nov 9, Proceedings - 2018 International Conference on Field-Programmable Logic and Applications, FPL 2018. Institute of Electrical and Electronics Engineers Inc., p. 239-242 4 p. 8533501. (Proceedings - 2018 International Conference on Field-Programmable Logic and Applications, FPL 2018).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Adaptive body bias control scheme for ultra low-power network-on-chip systems

Ben Ahmed, A., Okuhara, H., Matsutani, H., Koibuchi, M. & Amano, H., 2018 Nov 16, Proceedings - 2018 IEEE 12th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2018. Institute of Electrical and Electronics Engineers Inc., p. 146-153 8 p. 8540227

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Analysis of body bias control using overhead conditions for real time systems: A practical approach

Torres, C. C. C., Okuhara, H., Yamasaki, N. & Amano, H., 2018 Apr 1, In : IEICE Transactions on Information and Systems. E101D, 4, p. 1116-1125 10 p.

Research output: Contribution to journalArticle

1 Citation (Scopus)

An extension of a temperature modeling tool hotspot 6.0 for castle-of-chips stacking

Totoki, T., Koibuchi, M. & Amano, H., 2018 Dec 26, Proceedings - 2018 6th International Symposium on Computing and Networking Workshops, CANDARW 2018. Institute of Electrical and Electronics Engineers Inc., p. 363-369 7 p. 8590927. (Proceedings - 2018 6th International Symposium on Computing and Networking Workshops, CANDARW 2018).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

An inductive-coupling link for 3-D Network-on-Chips

Kadomoto, J., Amano, H. & Kuroda, T., 2018 May 29, Proceedings - International SoC Design Conference 2017, ISOCC 2017. Institute of Electrical and Electronics Engineers Inc., p. 150-151 2 p. (Proceedings - International SoC Design Conference 2017, ISOCC 2017).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

An trace-driven performance prediction method for exploring noc design optimization

Niwa, N., Totoki, T., Matsutani, H., Koibuchi, M. & Amano, H., 2018 Dec 26, Proceedings - 2018 6th International Symposium on Computing and Networking Workshops, CANDARW 2018. Institute of Electrical and Electronics Engineers Inc., p. 182-185 4 p. 8590896. (Proceedings - 2018 6th International Symposium on Computing and Networking Workshops, CANDARW 2018).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A Practical Collision Avoidance Method for an Inter-Chip Bus with Wireless Inductive through Chip Interface

Nomura, A., Kadomoto, JI., Kuroda, T. & Amano, H., 2018 Apr 23, Proceedings - 2017 5th International Symposium on Computing and Networking, CANDAR 2017. Institute of Electrical and Electronics Engineers Inc., Vol. 2018-January. p. 126-131 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Asymmetric Body Bias Control With Low-Power FD-SOI Technologies: Modeling and Power Optimization

Okuhara, H., Ben Ahmed, A., Kuhn, J. M. & Amano, H., 2018 Mar 23, (Accepted/In press) In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Research output: Contribution to journalArticle

9 Citations (Scopus)

AxNoC: Low-power Approximate Network-on-Chips using Critical-Path Isolation

Ahmed, A. B., Fujiki, D., Matsutani, H., Koibuchi, M. & Amano, H., 2018 Oct 26, 2018 12th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2018. Institute of Electrical and Electronics Engineers Inc., 8512158. (2018 12th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2018).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

11 Citations (Scopus)

Body Bias Control for Renewable Energy Source with a High Inner Resistance

Azegami, K., Okuhara, H. & Amano, H., 2018 Apr 16, (Accepted/In press) In : IEEE Transactions on Multi-Scale Computing Systems.

Research output: Contribution to journalArticle

Break even time analysis using empirical overhead parameters for embedded systems on SOTB technology

Cortes, C., Amano, H. & Yamasaki, N., 2018 Mar 9, 2017 32nd Conference on Design of Circuits and Integrated Systems, DCIS 2017 - Proceedings. Institute of Electrical and Electronics Engineers Inc., Vol. 2017-November. p. 1-6 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Building block multi-chip systems using inductive coupling through chip interface

Amano, H., Kuroda, T., Nakamura, H., Usami, K., Kondo, M., Matsutani, H. & Namiki, M., 2018 May 29, Proceedings - International SoC Design Conference 2017, ISOCC 2017. Institute of Electrical and Electronics Engineers Inc., p. 152-154 3 p. (Proceedings - International SoC Design Conference 2017, ISOCC 2017).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Building block operating system for 3D stacked computer systems with inductive coupling interconnect

Hamada, S., Koshiba, A., Namiki, M. & Amano, H., 2018 May 29, Proceedings - International SoC Design Conference 2017, ISOCC 2017. Institute of Electrical and Electronics Engineers Inc., p. 157-158 2 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

C4: An FPGA-based compression algorithm for expether

Shimura, H., Noda, H. & Amano, H., 2018 Dec 26, Proceedings - 2018 6th International Symposium on Computing and Networking Workshops, CANDARW 2018. Institute of Electrical and Electronics Engineers Inc., p. 356-362 7 p. 8590926. (Proceedings - 2018 6th International Symposium on Computing and Networking Workshops, CANDARW 2018).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Deep learning on high performance FPGA switching boards: Flow-in-cloud

Musha, K., Kudoh, T. & Amano, H., 2018 Jan 1, Applied Reconfigurable Computing: Architectures, Tools, and Applications - 14th International Symposium, ARC 2018, Proceedings. Springer Verlag, p. 43-54 12 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 10824 LNCS).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Design automation methodology of a critical path monitor for adaptive voltage controls

Kazami, R., Okuhara, H. & Amano, H., 2018 Jun 5, 21st IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL Chips 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc., p. 1-3 3 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Designing High-Performance Interconnection Networks with Host-Switch Graphs

Yasudo, R., Koibuchi, M., Nakano, K., Matsutani, H. & Amano, H., 2018 Aug 6, (Accepted/In press) In : IEEE Transactions on Parallel and Distributed Systems.

Research output: Contribution to journalArticle

1 Citation (Scopus)

Digital embedded memory scheme using voltage scaling and body bias separation for low-power system

Yoshida, Y., Usami, K. & Amano, H., 2018 May 29, Proceedings - International SoC Design Conference 2017, ISOCC 2017. Institute of Electrical and Electronics Engineers Inc., p. 148-149 2 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Digitally Assisted On-Chip Body Bias Tuning Scheme for Ultra Low-Power VLSI Systems

Okuhara, H., Ben Ahmed, A. & Amano, H., 2018 Mar 13, (Accepted/In press) In : IEEE Transactions on Circuits and Systems I: Regular Papers.

Research output: Contribution to journalArticle

4 Citations (Scopus)

Energy Efficient Write Verify and Retry Scheme for MTJ Based Flip-Flop and Application

Usami, K., Akaike, J., Akiba, S., Kudo, M., Amano, H., Ikezoe, T., Hiraga, K., Shuto, Y. & Yagami, K., 2018 Nov 15, Proceedings - 7th IEEE Non-Volatile Memory Systems and Applications Symposium, NVMSA 2018. Institute of Electrical and Electronics Engineers Inc., p. 91-98 8 p. 8537701. (Proceedings - 7th IEEE Non-Volatile Memory Systems and Applications Symposium, NVMSA 2018).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

FPGA-based accelerator for losslessly quantized convolutional neural networks

Sit, M., Kazami, R. & Amano, H., 2018 Feb 2, 2017 International Conference on Field-Programmable Technology, ICFPT 2017. Institute of Electrical and Electronics Engineers Inc., p. 295-298 4 p. (2017 International Conference on Field-Programmable Technology, ICFPT 2017; vol. 2018-January).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

FPGA Design for Autonomous Vehicle Driving Using Binarized Neural Networks

Wei, K., Honda, K. & Amano, H., 2018 Dec, Proceedings - 2018 International Conference on Field-Programmable Technology, FPT 2018. Institute of Electrical and Electronics Engineers Inc., p. 428-431 4 p. 8742321. (Proceedings - 2018 International Conference on Field-Programmable Technology, FPT 2018).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Glitch-aware variable pipeline optimization for CGRAs

Kojima, T., Ando, N., Okuhara, H. & Amano, H., 2018 Feb 2, 2017 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2017. Institute of Electrical and Electronics Engineers Inc., Vol. 2018-January. p. 1-6 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)