• 2575 Citations
  • 23 h-Index
1983 …2020

Research output per year

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Research Output

A high speed design and implementation of dynamically reconfigurable processor using 28NM SOI technology

Katagiri, T. & Amano, H., 2014 Oct 16, Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014. Institute of Electrical and Electronics Engineers Inc., 6927438. (Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

A high speed license plate recognition system on an FPGA

Kanamori, T., Amano, H., Arai, M., Konno, D., Nanba, T. & Ajioka, Y., 2007 Dec 1, Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL. p. 554-557 4 p. 4380715. (Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

A layout-oriented routing method for low-latency HPC networks

Kawano, R., Nakahara, H., Fujiwara, I., Matsutani, H., Koibuchi, M. & Amano, H., 2017 Dec, In : IEICE Transactions on Information and Systems. E100D, 12, p. 2796-2807 12 p.

Research output: Contribution to journalArticle

1 Citation (Scopus)

A leakage current monitor circuit using silicon on thin BOX MOSFET for dynamic back gate bias control

Okuhara, H., Usami, K. & Amano, H., 2015 Jul 14, IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips XVIII - Proceedings. Institute of Electrical and Electronics Engineers Inc., 7158656

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A leakage efficient data TLB design for embedded processors

Lei, Z., Xu, H., Ikebuchi, D., Sunata, T., Namiki, M. & Amano, H., 2011 Jan, In : IEICE Transactions on Information and Systems. E94-D, 1, p. 51-59 9 p.

Research output: Contribution to journalArticle

Open Access

A leakage efficient instruction TLB design for embedded processors

Lei, Z., Xu, H., Ikebuchi, D., Sunata, T., Namiki, M. & Amano, H., 2011 Aug, In : IEICE Transactions on Information and Systems. E94-D, 8, p. 1565-1574 10 p.

Research output: Contribution to journalArticle

A lightweight fault-tolerant mechanism for network-on-chip

Koibuchi, M., Matsutani, H., Amano, H. & Pinkston, T. M., 2008 May 28, Proceedings - Second IEEE International Symposium on Networks-on-Chip, NOCS 2008. p. 13-22 10 p. 4492721. (Proceedings - Second IEEE International Symposium on Networks-on-Chip, NOCS 2008).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

110 Citations (Scopus)

A link removal methodology for application-specific networks-on-chip on FPGAs

Wang, D., Matsutani, H., Koibuchi, M. & Amano, H., 2009 Jan 1, In : IEICE Transactions on Information and Systems. E92-D, 4, p. 575-583 9 p.

Research output: Contribution to journalArticle

A local area system network RHiNET-1: A network for high performance parallel computing

Nishi, H., Tasho, K., Yamamoto, J., Kudoh, T. & Amano, H., 2000 Jan 1, Proceedings - The 9th International Symposium on High-Performance Distributed Computing, HPDC 2000. Institute of Electrical and Electronics Engineers Inc., p. 296-297 2 p. 868665. (Proceedings of the IEEE International Symposium on High Performance Distributed Computing; vol. 2000-January).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

A low latency high bandwidth network interface prototype for PC cluster

Tanabe, N., Hamada, Y., Nakajo, H., Imashiro, H., Yamamoto, J., Kudoh, T. & Amano, H., 2002 Jan 1, International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems, IWIA 2002. Joe, K. & Veidenbaum, A. (eds.). IEEE Computer Society, p. 87-94 8 p. 1035022. (Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems; vol. 2002-January).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

A low-power fault-tolerant noc using error correction and detection codes

Kojima, Y., Matsutani, H., Koibuchi, M. & Amano, H., 2010 Jan 1, Proceedings of the 9th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2010. Acta Press, p. 111-118 8 p. (Proceedings of the 9th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2010).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A low power NoC router using the marching memory through type

Yasudo, R., Kagami, T., Amano, H., Nakase, Y., Watanebe, M., Oishi, T., Shimizu, T. & Nakamura, T., 2014 Jan 1, IEEE Symposium on Low-Power and High-Speed Chips - Proceedings for 2014 IEEE COOL Chips XVII. IEEE Computer Society, 6842960. (IEEE Symposium on Low-Power and High-Speed Chips - Proceedings for 2014 IEEE COOL Chips XVII).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A low power reconfigurable accelerator using a back-gate bias control technique

Su, H., Wang, W., Kitamori, K. & Amano, H., 2013 Dec 1, FPT 2013 - Proceedings of the 2013 International Conference on Field Programmable Technology. p. 390-393 4 p. 6718395. (FPT 2013 - Proceedings of the 2013 International Conference on Field Programmable Technology).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

A mapping method for multi-process execution on dynamically reconfigurable processors

Vu, M. T. & Amano, H., 2007 Dec 1, ICFPT 2007 - International Conference on Field Programmable Technology. p. 357-360 4 p. 4439285. (ICFPT 2007 - International Conference on Field Programmable Technology).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

A mapping method for multi-process execution on dynamically reconfigurable processors

Manh Tuan, V. & Amano, H., 2008 Sep, In : IEICE Transactions on Information and Systems. E91-D, 9, p. 2312-2322 11 p.

Research output: Contribution to journalArticle

4 Citations (Scopus)

A metamorphotic Network-on-Chip for various types of parallel applications

Tade, S., Matsutani, H., Amano, H. & Koibuchi, M., 2015 Sep 8, Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors. Institute of Electrical and Electronics Engineers Inc., Vol. 2015-September. p. 98-105 8 p. 7245715

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A method for capturing state data on dynamically reconfigurable processors

Tuan, V. M. & Amano, H., 2008 Dec 1, Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2008. p. 208-214 7 p. (Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2008).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

A modular approach to heterogeneous biochemical model simulation on an FPGA

Yamada, H., Osana, Y., Ishimori, T., Ooya, T., Yoshimi, M., Nishikawa, Y., Funahashi, A., Hiroi, N., Amano, H., Shibata, Y. & Oguri, K., 2009 Dec 1, ReConFig'09 - 2009 International Conference on ReConFigurable Computing and FPGAs. p. 125-130 6 p. 5382039. (ReConFig'09 - 2009 International Conference on ReConFigurable Computing and FPGAs).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

A multi-Vdd dynamic variable-pipeline on-chip router for CMPs

Matsutani, H., Hirata, Y., Koibuchi, M., Usami, K., Nakamura, H. & Amano, H., 2012 Apr 26, ASP-DAC 2012 - 17th Asia and South Pacific Design Automation Conference. p. 407-412 6 p. 6164982. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

14 Citations (Scopus)

An adaptable cluster structure of (SM)2 -II

Saito, C., Amano, H., Kudoh, T. & Aiso, H., 1986 Jan 1, CONPAR 1986 - Conference on Algorithms and Hardware for Parallel Processing, Proceedings. Handler, W., Jeltsch, R., Lange, O., Haupt, D. & Juling, W. (eds.). Springer Verlag, p. 53-60 8 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 237 LNCS).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

An adaptive cryptographic accelerator for IPsec on dynamically reconfigurable processor

Hasegawa, Y., Abe, S., Matsutani, H., Amano, H., Anjo, K. & Awashima, T., 2005 Dec 1, Proceedings - 2005 IEEE International Conference on Field Programmable Technology. p. 163-170 8 p. 1568541. (Proceedings - 2005 IEEE International Conference on Field Programmable Technology; vol. 2005).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

16 Citations (Scopus)

An adaptive Viterbi decoder on the dynamically reconfigurable processor

Abe, S., Hasegawa, Y., Toi, T., Inuo, T. & Amano, H., 2006 Dec 1, Proceedings - 2006 IEEE International Conference on Field Programmable Technology, FPT 2006. p. 285-288 4 p. 4042451. (Proceedings - 2006 IEEE International Conference on Field Programmable Technology, FPT 2006).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Analysis of body bias control using overhead conditions for real time systems: A practical approach

Torres, C. C. C., Okuhara, H., Yamasaki, N. & Amano, H., 2018 Apr 1, In : IEICE Transactions on Information and Systems. E101D, 4, p. 1116-1125 10 p.

Research output: Contribution to journalArticle

1 Citation (Scopus)

An analysis of fairness and overhead in the arbitration protocol of the IEEE futurebus standard

Yamamoto, O., Terasawa, T. & Amano, H., 1998 Nov 30, In : Systems and Computers in Japan. 29, 13, p. 66-77 12 p.

Research output: Contribution to journalArticle

An analytical network performance model for SIMD processor CSX600 interconnects

Nishikawa, Y., Koibuchi, M., Yoshimi, M., Miura, K. & Amano, H., 2011 Jan 1, In : Journal of Systems Architecture. 57, 1, p. 146-159 14 p.

Research output: Contribution to journalArticle

An ARM-based heterogeneous FPGA accelerator for hall thruster simulation

Noda, H., Orsztynowicz, M., Iizuka, K., Miyajima, T., Fujita, N. & Amano, H., 2019 Jun 6, Proceedings of the 10th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, HEART 2019. Association for Computing Machinery, 9. (ACM International Conference Proceeding Series).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

An educational system of LSI design with free-wares for VDEC

Morisawa, F., Kawakami, D., Tanaka, K. & Amano, H., 1999 Jan 1, Proceedings - 1999 IEEE International Conference on Microelectronic Systems Education: Systems Education in the 21st Century, MSE 1999. Institute of Electrical and Electronics Engineers Inc., p. 61-62 2 p. 787038

Research output: Chapter in Book/Report/Conference proceedingConference contribution

An effective design of deadlock-free routing algorithms based on 2D turn model for irregular networks

Jouraku, A., Koibuchi, M. & Amano, H., 2007 Mar 1, In : IEEE Transactions on Parallel and Distributed Systems. 18, 3, p. 320-333 14 p.

Research output: Contribution to journalArticle

26 Citations (Scopus)

An emulation system of the WASMII: A data driven computer on a virtual hardware

Shibata, Y., Ling, X. P. & Amano, H., 1996, Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Springer Verlag, Vol. 1142. p. 55-64 10 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 1142).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

A network switch for supporting high-performance parallel processing by computers distributed in local areas

Nishi, H., Tasho, K., Kudoh, T. & Amano, H., 2001 Dec 1, In : Systems and Computers in Japan. 32, 14, p. 24-33 10 p.

Research output: Contribution to journalArticle

A network switch using optical interconnection for high performance parallel computing using PCs: High-density implementation of high-speed signals for a one-chip electronic switch with optical interconnections

Nishimura, S., Kudoh, T., Nishi, H., Harasawa, K., Matsudaira, N., Akutsu, S., Tasyo, K. & Amano, H., 1999 Jan 1, Proceedings - 6th International Conference on Parallel Interconnects, PI 1999. Schenfeld, E., Kostuk, R., Lund, C. & Haney, M. (eds.). Institute of Electrical and Electronics Engineers Inc., p. 5-12 8 p. 806389. (Proceedings - 6th International Conference on Parallel Interconnects, PI 1999).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

A new memory module for COTS-based personal supercomputing

Tanabe, N., Nakatake, M., Hakozaki, H., Dohi, Y., Nakajo, H. & Amano, H., 2004 Dec 1, p. 40-48. 9 p.

Research output: Contribution to conferencePaper

11 Citations (Scopus)

A new memory module for memory intensive applications

Tanabe, N., Hakozaki, H., Nakatake, M., Dohi, Y., Nakajo, H. & Amano, H., 2004 Dec 1, International Conference on Parallel Computing in Electrical Engineering: Workshop on System Design Automation, SDA, PARELEC 2004. p. 123-128 6 p. (International Conference on Parallel Computing in Electrical Engineering: Workshop on System Design Automation, SDA, PARELEC 2004).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

A new version of a parallel production system machine, MANJI-II

Miyazaki, J., Takeda, K., Amano, H. & Aiso, H., 1989, Database Machines - 6th International Workshop, IWDM 1989, Proceedings. Springer Verlag, Vol. 368 LNCS. p. 317-330 14 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 368 LNCS).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

An extension of a temperature modeling tool hotspot 6.0 for castle-of-chips stacking

Totoki, T., Koibuchi, M. & Amano, H., 2018 Dec 26, Proceedings - 2018 6th International Symposium on Computing and Networking Workshops, CANDARW 2018. Institute of Electrical and Electronics Engineers Inc., p. 363-369 7 p. 8590927. (Proceedings - 2018 6th International Symposium on Computing and Networking Workshops, CANDARW 2018).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

An FPGA acceleration for the kd-tree search in photon mapping

Kuhara, T., Miyajima, T., Yoshimi, M. & Amano, H., 2013 Apr 3, Reconfigurable Computing: Architectures, Tools, and Applications - 9th International Symposium, ARC 2013, Proceedings. p. 25-36 12 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 7806 LNCS).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

An FPGA-based, multi-model simulation method for biochemical systems

Osana, Y., Fukushima, T., Yoshimi, M., Iwaoka, Y., Funahashi, A., Hiroi, N., Shibata, Y., Kitano, H. & Amano, H., 2005 Dec 1, Proceedings - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005. 1420035. (Proceedings - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005; vol. 2005).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

An FPGA-based acceleration method for metabolic simulation

Osana, Y., Fukushima, T., Yoshimi, M. & Amano, H., 2004 Aug, In : IEICE Transactions on Information and Systems. E87-D, 8, p. 2029-2037 9 p.

Research output: Contribution to journalReview article

4 Citations (Scopus)

An FPGA implementation of high throughput stochastic simulator for large-scale biochemical systems

Yoshimi, M., Osana, Y., Iwaoka, Y., Nishikawa, Y., Kojima, T., Shibata, Y., Iwanaga, N., Funahashi, A., Hiroi, N., Kitano, H. & Amano, H., 2006 Dec 1, Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL. p. 227-232 6 p. 4100980. (Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

An FPGA implementation of reconfigurable real-time vision architecture

Hiraiwa, J. & Amano, H., 2013 Aug 19, Proceedings - 27th International Conference on Advanced Information Networking and Applications Workshops, WAINA 2013. p. 150-155 6 p. 6550388. (Proceedings - 27th International Conference on Advanced Information Networking and Applications Workshops, WAINA 2013).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

15 Citations (Scopus)

An I/O mechanism on a dynamically reconfigurable processor - Which should be moved: Data or configuration?

Amano, H., Abe, S., Deguchi, K. & Hasegawa, Y., 2005 Dec 1, Proceedings - 2005 International Conference on Field Programmable Logic and Applications, FPL. p. 347-352 6 p. 1515746. (Proceedings - 2005 International Conference on Field Programmable Logic and Applications, FPL; vol. 2005).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

An implementation of the Rijndael on Async-WASMII

Adachi, Y., Ishikawa, K., Tsutsumi, S. & Amano, H., 2003 Jan 1, Proceedings - 2003 IEEE International Conference on Field-Programmable Technology, FPT 2003. Institute of Electrical and Electronics Engineers Inc., p. 44-51 8 p. 1275730. (Proceedings - 2003 IEEE International Conference on Field-Programmable Technology, FPT 2003).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

An inductive-coupling bus with collision detection scheme using magnetic field variation for 3-D network-on-chips

Kadomoto, J., Miyata, T., Amano, H. & Kuroda, T., 2017 Feb 6, 2016 IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 - Proceedings. Institute of Electrical and Electronics Engineers Inc., p. 41-44 4 p. 7844130

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

An inductive-coupling link for 3-D Network-on-Chips

Kadomoto, J., Amano, H. & Kuroda, T., 2018 May 29, Proceedings - International SoC Design Conference 2017, ISOCC 2017. Institute of Electrical and Electronics Engineers Inc., p. 150-151 2 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

An on/off link activation method for low-power ethernet in PC clusters

Koibuchi, M., Otsuka, T., Matsutani, H. & Amano, H., 2009 Nov 25, IPDPS 2009 - Proceedings of the 2009 IEEE International Parallel and Distributed Processing Symposium. 5161069. (IPDPS 2009 - Proceedings of the 2009 IEEE International Parallel and Distributed Processing Symposium).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Citations (Scopus)

An OpenCL runtime library for embedded multi-core accelerator

Sakamoto, R., Sato, M., Koizumi, Y., Amano, H. & Namiki, M., 2012 Nov 19, p. 419-422. 4 p.

Research output: Contribution to conferencePaper

1 Citation (Scopus)

An operating system guided fine-grained power gating control based on runtime characteristics of applications

Koshiba, A., Sato, M., Usami, K., Amano, H., Sakamoto, R., Kondo, M., Nakamura, H. & Namiki, M., 2016 Aug 1, In : IEICE Transactions on Electronics. E99C, 8, p. 926-935 10 p.

Research output: Contribution to journalArticle

An optimal power supply and body bias voltage for a ultra low power micro-controller with silicon on thin box MOSFET

Okuhara, H., Kitamori, K., Fujita, Y., Usami, K. & Amano, H., 2015 Sep 21, Proceedings of the International Symposium on Low Power Electronics and Design. Institute of Electrical and Electronics Engineers Inc., Vol. 2015-September. p. 207-212 6 p. 7273515

Research output: Chapter in Book/Report/Conference proceedingConference contribution

13 Citations (Scopus)

A novel channel assignment method to ensure deadlock-freedom for deterministic routing

Kawano, R., Nakahara, H., Tade, S., Fujiwara, I., Matsutani, H., Koibuchi, M. & Amano, H., 2017 Aug, In : IEICE Transactions on Information and Systems. E100D, 8, p. 1798-1806 9 p.

Research output: Contribution to journalArticle

2 Citations (Scopus)