• 2613 Citations
  • 23 h-Index
1983 …2020

Research output per year

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Research Output

DIMMnet-2: A reconfigurable board connected into a memory slot

Miyashiro, T., Kitamura, A., Yoshimi, M., Amano, H., Nakajyo, H. & Tanabe, N., 2006 Dec 1, Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL. p. 825-828 4 p. 4101085. (Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

DIPROS - A DISTRIBUTED PROCESSING SYSTEM FOR NDL ON (SM)**2-II.

Boku, T., Kudoh, T., Amano, H. & Aiso, H., 1987 Jan 1, In : Proceedings of the Hawaii International Conference on System Science. 2, p. 208-217 10 p.

Research output: Contribution to journalConference article

1 Citation (Scopus)

Distributed shared memory architecture for JUMP-1: A general-purpose MPP prototype

Matsumoto, T., Kudoh, T., Nishimura, K., Hiraki, K., Amano, H. & Tanaka, H., 1996 Jan 1, p. 131-137. 7 p.

Research output: Contribution to conferencePaper

5 Citations (Scopus)

D-tdma data buses with CSMA/CD arbitration bus on wireless 3D IC

Matsumura, G., Koibuchi, M., Amano, H. & Matsutani, H., 2016, Proceedings of the 13th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2016. Acta Press, p. 242-249 8 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Dynamically reconfigurable flux limiter functions in MUSCL scheme

Talip, M. S. A., Akamine, T., Osana, Y., Fujita, N. & Amano, H., 2012 Nov 23, ReCoSoC 2012 - 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip, Proceedings. 6322878. (ReCoSoC 2012 - 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip, Proceedings).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Dynamic fault recovery in mesh‐connected parallel computers

Yokota, T., Amano, H. & Aiso, H., 1986, In : Systems and Computers in Japan. 17, 7, p. 10-18 9 p.

Research output: Contribution to journalArticle

Dynamic power consumption optimization for inductive-coupling based wireless 3D NoCs

Zhang, H., Matsutani, H., Koibuchi, M. & Amano, H., 2014 Feb 1, In : IPSJ Transactions on System LSI Design Methodology. 7, p. 27-36 10 p.

Research output: Contribution to journalArticle

2 Citations (Scopus)

Dynamic power control with a heterogeneous multi-core system using a 3-D wireless inductive coupling interconnect

Koizumi, Y., Amano, H., Matsutani, H., Miura, N., Kuroda, T., Sakamoto, R., Namiki, M., Usami, K., Kondo, M. & Nakamura, H., 2012 Dec 1, FPT 2012 - 2012 International Conference on Field-Programmable Technology. p. 293-296 4 p. 6412150. (FPT 2012 - 2012 International Conference on Field-Programmable Technology).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Dynamic power on/off method for 3D NoCs with wireless inductive-coupling links

Zhang, H., Matsutani, H., Koibuchi, M. & Amano, H., 2013 Aug 15, IEEE Symposium on Low-Power and High-Speed Chips - Proceedings for 2013 COOL Chips XVI. 6547924. (IEEE Symposium on Low-Power and High-Speed Chips - Proceedings for 2013 COOL Chips XVI).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Dynamic VDD switching technique and mapping optimization in dynamically reconfigurable processor for efficient energy reduction

Yamamoto, T., Hironaka, K., Hayakawa, Y., Kimura, M., Amano, H. & Usami, K., 2011 Apr 4, Reconfigurable Computing: Architectures, Tools and Applications - 7th International Symposium, ARC 2011, Proceedings. p. 230-241 12 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 6578 LNCS).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Citations (Scopus)

Efficient 3-D Bus Architectures for Inductive-Coupling ThruChip Interfaces

Kagami, T., Matsutani, H., Koibuchi, M., Take, Y., Kuroda, T. & Amano, H., 2016 Feb, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 24, 2, p. 493-506 14 p., 7086053.

Research output: Contribution to journalArticle

15 Citations (Scopus)

Efficient scheduling of rate law functions for ODE-based multimodel biochemical simulation on an FPGA

Iwanagra, N., Shibata, Y., Yoshimi, M., Osana, Y., Iwaoka, Y., Fukushima, T., Amano, H., Funahashi, A., Hiroi, N., Kitano, H. & Oguri, K., 2005 Dec 1, Proceedings - 2005 International Conference on Field Programmable Logic and Applications, FPL. p. 666-669 4 p. 1515809. (Proceedings - 2005 International Conference on Field Programmable Logic and Applications, FPL; vol. 2005).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Citations (Scopus)

Embedded software compression with split echo instructions

Stubdal, I., Karaduman, A. & Amano, H., 2009 Oct 27, 2009 IEEE 13th International Symposium on Consumer Electronics, ISCE 2009. p. 816-818 3 p. 5157058. (Digest of Technical Papers - IEEE International Conference on Consumer Electronics).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Energy Efficient Write Verify and Retry Scheme for MTJ Based Flip-Flop and Application

Usami, K., Akaike, J., Akiba, S., Kudo, M., Amano, H., Ikezoe, T., Hiraga, K., Shuto, Y. & Yagami, K., 2018 Nov 15, Proceedings - 7th IEEE Non-Volatile Memory Systems and Applications Symposium, NVMSA 2018. Institute of Electrical and Electronics Engineers Inc., p. 91-98 8 p. 8537701. (Proceedings - 7th IEEE Non-Volatile Memory Systems and Applications Symposium, NVMSA 2018).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Enforcing dimension-order routing in on-chip torus networks without virtual channels

Matsutani, H., Koibuchi, M. & Amano, H., 2006, Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Springer Verlag, Vol. 4330. p. 207-218 12 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 4330).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

ESPRIT/sim: A high speed performance-simulator for heterogeneous embedded multiprocessors

Ohmiya, Y. & Amano, H., 2008 Dec 1, Proceedings of the 20th IASTED International Conference on Parallel and Distributed Computing and Systems, PDCS 2008. p. 252-257 6 p. (Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Systems).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Evaluation of a multicore reconfigurable architecture with variable core sizes

Tuan, V. M., Katsura, N., Matsutani, H. & Amano, H., 2009 Nov 25, IPDPS 2009 - Proceedings of the 2009 IEEE International Parallel and Distributed Processing Symposium. 5161225. (IPDPS 2009 - Proceedings of the 2009 IEEE International Parallel and Distributed Processing Symposium).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Evaluation of MuCCRA-D: A dynamically reconfigurable processor with directly interconnected PEs

Kato, M., Hasegawa, Y. & Amano, H., 2008 Dec 1, Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2008. p. 215-221 7 p. (Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2008).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Evaluation of network interface controller on DIMMnet-2 prototype board

Kitamura, A., Hamada, Y., Miyabe, Y., Izawa, T., Miyashiro, T., Watanabe, K., Otsuka, T., Tanabe, N., Nakajo, H. & Amano, H., 2005 Dec 1, Proceedings - Sixth International Conference on Parallel and Distributed Computing, Applications and Technologies, PDCAT 2005. p. 778-780 3 p. 1579028. (Parallel and Distributed Computing, Applications and Technologies, PDCAT Proceedings; vol. 2005).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Expandable Chip Stacking Method for Many-core Architectures Consisting of Tiny Chips

Nakahara, H., Ozaki, T., Matsutani, H., Koibuchi, M. & Amano, H., 2015 Nov 11, Proceedings - IEEE 9th International Symposium on Embedded Multicore/Manycore SoCs, MCSoC 2015. Institute of Electrical and Electronics Engineers Inc., p. 41-48 8 p. 7328185

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Exploiting memory hierarchy for a Computational Fluid Dynamics accelerator on FPGAs

Morishita, H., Osana, Y., Fujita, N. & Amano, H., 2008 Dec 1, Proceedings of the 2008 International Conference on Field-Programmable Technology, ICFPT 2008. p. 193-200 8 p. 4762383. (Proceedings of the 2008 International Conference on Field-Programmable Technology, ICFPT 2008).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Citations (Scopus)

Exploring the optimal size for multicasting configuration data of dynamically Reconfigurable processors

Nakamura, T., Sano, T., Hasegawa, Y., Tsutsumi, S., Tunbunheng, V. & Amano, H., 2008 Dec 1, Proceedings of the 2008 International Conference on Field-Programmable Technology, ICFPT 2008. p. 137-144 8 p. 4762376. (Proceedings of the 2008 International Conference on Field-Programmable Technology, ICFPT 2008).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Extension of memory controller equipped with MuCCRA-3-DP: Dynamically reconfigurable processor array

Katagiri, T., Hironaka, K. & Amano, H., 2012 Dec 14, Proceedings of the 2012 15th International Conference on Network-Based Information Systems, NBIS 2012. p. 826-831 6 p. 6354932. (Proceedings of the 2012 15th International Conference on Network-Based Information Systems, NBIS 2012).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Fat H-Tree: A cost-efficient tree-based on-chip network

Matsutani, H., Koibuchi, M., Yamada, Y., Hsu, D. F. & Amano, H., 2009 Jun 4, In : IEEE Transactions on Parallel and Distributed Systems. 20, 8, p. 1126-1141 16 p.

Research output: Contribution to journalArticle

18 Citations (Scopus)

Fault tolerance of the TBSF (Tandem Banyan Switching Fabrics) and PBSF (Piled Banyan Switching Fabrics)

Funahashi, A., Hanawa, T. & Amano, H., 1996 Jan 1, In : IEICE Transactions on Information and Systems. E79-D, 8, p. 1180-1189 10 p.

Research output: Contribution to journalArticle

Fined-grained body biasing for frequency scaling in advanced SOI processes

Kuhn, J. M., Amano, H., Bringmann, O. & Rosenstiel, W., 2015 Jul 14, IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips XVIII - Proceedings. Institute of Electrical and Electronics Engineers Inc., 7158655

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Fine-grained power control using a multi-voltage variable pipeline router

Nakamura, T., Matsutani, H., Koibuchi, M., Usami, K. & Amano, H., 2012 Dec 1, p. 59-66. 8 p.

Research output: Contribution to conferencePaper

4 Citations (Scopus)

Fine-grained run-tume power gating through co-optimization of circuit, architecture, and system software design

Nakamura, H., Wang, W., Ohta, Y., Usami, K., Amano, H., Kondo, M. & Namiki, M., 2013 Apr, In : IEICE Transactions on Electronics. E96-C, 4, p. 404-412 9 p.

Research output: Contribution to journalArticle

Fine grain partial reconfiguration for energy saving in dynamically reconfigurable processors

Sano, T., Saito, Y., Kato, M. & Amano, H., 2009 Nov 25, FPL 09: 19th International Conference on Field Programmable Logic and Applications. p. 530-533 4 p. 5272435. (FPL 09: 19th International Conference on Field Programmable Logic and Applications).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Folded fat H-Tree: An interconnection topology for dynamically reconfigurable processor array

Yamada, Y., Amano, H., Koibuchi, M., Jouraku, A., Anjo, K. & Nishimura, K., 2004 Jan 1, Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Yang, L. T., Guo, M., Gao, G. R. & Jha, N. K. (eds.). Springer Verlag, p. 301-311 11 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 3207).

Research output: Chapter in Book/Report/Conference proceedingChapter

3 Citations (Scopus)

Fpga/python co-design for lane line detection on a pynq-z1 board

Honda, K., Wei, K. & Amano, H., 2019 Oct, Proceedings - 2019 IEEE 13th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019. Institute of Electrical and Electronics Engineers Inc., p. 53-60 8 p. 8906682. (Proceedings - 2019 IEEE 13th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

FPGA-based accelerator for losslessly quantized convolutional neural networks

Sit, M., Kazami, R. & Amano, H., 2018 Feb 2, 2017 International Conference on Field-Programmable Technology, ICFPT 2017. Institute of Electrical and Electronics Engineers Inc., p. 295-298 4 p. (2017 International Conference on Field-Programmable Technology, ICFPT 2017; vol. 2018-January).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

FPGA-based HPRC for bioinformatics applications

Yamaguchi, Y., Osana, Y., Yoshimi, M. & Amano, H., 2014 Mar 1, High-Performance Computing Using FPGAs. Springer New York, Vol. 9781461417910. p. 137-175 39 p.

Research output: Chapter in Book/Report/Conference proceedingChapter

FPGA Design for Autonomous Vehicle Driving Using Binarized Neural Networks

Wei, K., Honda, K. & Amano, H., 2018 Dec, Proceedings - 2018 International Conference on Field-Programmable Technology, FPT 2018. Institute of Electrical and Electronics Engineers Inc., p. 428-431 4 p. 8742321. (Proceedings - 2018 International Conference on Field-Programmable Technology, FPT 2018).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

FPGA implementation of a data-driven stochastic biochemical simulator with the next reaction method

Yoshimi, M., Iwaoka, Y., Nishikawa, Y., Kojima, T., Osana, Y., Funahashi, A., Hiroi, N., Shibata, Y., Iwanaga, N., Yamada, H., Kitano, H. & Amano, H., 2007 Dec 1, Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL. p. 254-259 6 p. 4380656. (Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

14 Citations (Scopus)

FPGA implementation of viscous function in a package for computational fluid dynamics

Mishra, D., Hatto, M., Kuhara, T., Fujita, N., Osana, Y. & Amano, H., 2015 Feb 27, Proceedings - 2014 2nd International Symposium on Computing and Networking, CANDAR 2014. Institute of Electrical and Electronics Engineers Inc., p. 608-610 3 p. 7052258. (Proceedings - 2014 2nd International Symposium on Computing and Networking, CANDAR 2014).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

From FLOPS to BYTES: Disruptive change in high-performance computing towards the post-moore era

Matsuoka, S., Amano, H., Nakajima, K., Inoue, K., Kudoh, T., Maruyama, N., Taura, K., Iwashita, T., Katagiri, T., Hanawa, T. & Endo, T., 2016 May 16, 2016 ACM International Conference on Computing Frontiers - Proceedings. Association for Computing Machinery, Inc, p. 274-281 8 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Geyser-1: A MIPS R3000 CPU core with fine-grained run-time power gating

Ikebuchi, D., Seki, N., Kojima, Y., Kamata, M., Zhao, L., Amano, H., Shirai, T., Koyama, S., Hashida, T., Umahashi, Y., Masuda, H., Usami, K., Takeda, S., Nakamura, H., Namiki, M. & Kondo, M., 2010, 2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010. p. 369-370 2 p. 5419857. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Geyser-1: A MIPS R3000 CPU core with fine grain runtime power gating

Ikebuchi, D., Seki, N., Kojima, Y., Kamata, M., Zhao, L., Amano, H., Shirai, T., Koyamat, S., Hashida, T., Umahashi, Y., Masuda, H., Usami, K., Takeda, S., Nakamura, H., Namiki, M. & Kondo, M., 2009 Dec 1, Proceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009. p. 281-284 4 p. 5357257. (Proceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

33 Citations (Scopus)

Geyser-2: The second prototype CPU with fine-grained run-time power gating

Zhao, L., Ikebuchi, D., Saito, Y., Kamata, M., Seki, N., Kojima, Y., Amano, H., Koyama, S., Hashida, T., Umahashi, Y., Masuda, D., Usami, K., Kimura, K., Namiki, M., Takeda, S., Nakamura, H. & Kondo, M., 2011 Mar 28, 2011 16th Asia and South Pacific Design Automation Conference, ASP-DAC 2011. p. 87-88 2 p. 5722310. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Citations (Scopus)

Glitch-aware variable pipeline optimization for CGRAs

Kojima, T., Ando, N., Okuhara, H. & Amano, H., 2018 Feb 2, 2017 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2017. Institute of Electrical and Electronics Engineers Inc., Vol. 2018-January. p. 1-6 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

GPU-accelerated language and communication support by FPGA

Boku, T., Hanawa, T., Murai, H., Nakao, M., Miki, Y., Amano, H. & Umemura, M., 2018 Dec 6, Advanced Software Technologies for Post-Peta Scale Computing: The Japanese Post-Peta CREST Research Project. Springer Singapore, p. 301-317 17 p.

Research output: Chapter in Book/Report/Conference proceedingChapter

Guest editors' introduction ICFPT 2007

Amano, H. & Nakamura, T., 2009 Jun, In : ACM Transactions on Reconfigurable Technology and Systems. 2, 2, 7.

Research output: Contribution to journalEditorial

Hardware/software co-design architecture for Blokus Duo solver

Sugimoto, N. & Amano, H., 2014, Proceedings of the 2014 International Conference on Field-Programmable Technology, FPT 2014. Institute of Electrical and Electronics Engineers Inc., p. 358-361 4 p. 7082820

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Hardware support for MPI in DIMMnet-2 network interface

Tanabe, N., Kitamura, A., Miyashiro, T., Miyabe, Y., Araki, T., Luo, Z., Nakajo, H. & Amano, H., 2006 Dec 1, Proceedings - International Workshop on Innovative Architecture for Future Generation High Performance Processors and Systems, IWIA 2006. p. 73-80 8 p. 4089358. (Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Headfirst sliding routing: A time-based routing scheme for bus-NoC hybrid 3-D architecture

Kagami, T., Matsutani, H., Koibuchi, M. & Amano, H., 2013 Aug 19, 2013 7th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2013. 6558406. (2013 7th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2013).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)
2 Citations (Scopus)

High-Bandwidth Low-Latency Approximate Interconnection Networks

Fujiki, D., Ishii, K., Fujiwara, I., Matsutani, H., Amano, H., Casanova, H. & Koibuchi, M., 2017 May 5, Proceedings - 2017 IEEE 23rd Symposium on High Performance Computer Architecture, HPCA 2017. IEEE Computer Society, p. 469-480 12 p. 7920848

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Citations (Scopus)