• 2598 Citations
  • 23 h-Index
1983 …2020

Research output per year

If you made any changes in Pure these will be visible here soon.

Research Output

Chapter

GPU-accelerated language and communication support by FPGA

Boku, T., Hanawa, T., Murai, H., Nakao, M., Miki, Y., Amano, H. & Umemura, M., 2018 Dec 6, Advanced Software Technologies for Post-Peta Scale Computing: The Japanese Post-Peta CREST Research Project. Springer Singapore, p. 301-317 17 p.

Research output: Chapter in Book/Report/Conference proceedingChapter

Implementation of ReCSiP: A ReConfigurable cell SImulation Platform

Osana, Y., Fukushima, T. & Amano, H., 2003, Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Cheung, P. Y. K., Constantinides, G. A. & de Sousa, J. T. (eds.). Springer Verlag, p. 766-775 10 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 2778).

Research output: Chapter in Book/Report/Conference proceedingChapter

4 Citations (Scopus)

Reducing the configuration loading time of a coarse grain multicontext reconfigurable device

Kitaoka, T., Amano, H. & Anjo, K., 2003, Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Cheung, P. Y. K., Constantinides, G. A. & de Sousa, J. T. (eds.). Springer Verlag, p. 171-180 10 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 2778).

Research output: Chapter in Book/Report/Conference proceedingChapter

15 Citations (Scopus)

Run-time power-gating techniques for low-power on-chip networks

Matsutani, H., Koibuchi, M., Nakamura, H. & Amano, H., 2011 Dec 1, Low Power Networks-On-Chip. Springer, p. 21-43 23 p.

Research output: Chapter in Book/Report/Conference proceedingChapter

Stochastic simulation for biochemical reactions on FPGA

Yoshimi, M., Osana, Y., Fukushima, T. & Amano, H., 2004 Jan 1, Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Becker, J., Platzner, M. & Vernalde, S. (eds.). Springer Verlag, p. 105-114 10 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 3203).

Research output: Chapter in Book/Report/Conference proceedingChapter

19 Citations (Scopus)

Techniques for virtual hardware on a dynamically reconfigurable processor - An approach to tough cases

Amano, H., Inuo, T., Kami, H., Fujii, T. & Suzuki, M., 2004 Jan 1, Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Becker, J., Platzner, M. & Vernalde, S. (eds.). Springer Verlag, p. 464-473 10 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 3203).

Research output: Chapter in Book/Report/Conference proceedingChapter

13 Citations (Scopus)
Conference article

A concurrent program restructuring system for scientific calculations

Kimura, T., Boku, T., Kudoh, T. & Amano, H., 1991 Jan 1, In : Proceedings of the Annual Hawaii International Conference on System Sciences. 2, p. 390-399 10 p., 184001.

Research output: Contribution to journalConference article

Cache coherency protocol for multiprocessor chip

Terasawa, T., Ogura, S., Inoue, K. & Amano, H., 1995 Jan 1, In : Proceedings of the Annual IEEE International Conference on Innovative Systems in Silicon. p. 238-247 10 p.

Research output: Contribution to journalConference article

5 Citations (Scopus)

Cache controller design on ultra low leakage embedded processors

Lei, Z., Xu, H., Seki, N., Yoshiki, S., Hasegawa, Y., Usami, K. & Amano, H., 2009 Apr 6, In : Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 5455 LNCS, p. 171-182 12 p.

Research output: Contribution to journalConference article

DIPROS - A DISTRIBUTED PROCESSING SYSTEM FOR NDL ON (SM)**2-II.

Boku, T., Kudoh, T., Amano, H. & Aiso, H., 1987 Jan 1, In : Proceedings of the Hawaii International Conference on System Science. 2, p. 208-217 10 p.

Research output: Contribution to journalConference article

1 Citation (Scopus)

High-throughput network switch for the RHiNET-2 optically interconnected parallel computing system

Nishimura, S., Kudoh, T., Nishi, H., Harasawa, K., Matsudaira, N., Akutsu, S., Tasyo, K. & Amano, H., 2000 Jan 1, In : Proceedings of SPIE - The International Society for Optical Engineering. 4089, p. 562-569 8 p.

Research output: Contribution to journalConference article

3 Citations (Scopus)

Hot spot contention and message combining in the simple serial synchronized multistage interconnection network

Hanawa, T., Fujiwara, T. & Amano, H., 1996 Dec 1, In : IEEE Symposium on Parallel and Distributed Processing - Proceedings. p. 298-305 8 p.

Research output: Contribution to journalConference article

1 Citation (Scopus)

JUMP-1 router chip: A versatile router for supporting a distributed shared memory

Nishi, H., Nishimura, K., Anjo, K. I., Kudoh, T. & Amano, H., 1996 Jan 1, In : Conference Proceedings - International Phoenix Conference on Computers and Communications. p. 158-164 7 p.

Research output: Contribution to journalConference article

1 Citation (Scopus)

MANJI: AN ARCHITECTURE FOR PRODUCTION SYSTEMS.

Miyazaki, J., Amano, H. & Aiso, H., 1987 Jan 1, In : Proceedings of the Hawaii International Conference on System Science. 1, p. 236-245 10 p.

Research output: Contribution to journalConference article

4 Citations (Scopus)

New structure for rolling mapping

Murata, A. & Amano, H., 2000 Dec 1, In : Advances in High Performance Computing. 6, p. 233-245 13 p.

Research output: Contribution to journalConference article

Non-minimal routing strategy for application-specific Networks-on-Chips

Matsutani, H., Koibuchi, M., Yamada, Y., Jouraku, A. & Amano, H., 2005 Dec 1, In : Proceedings of the International Conference on Parallel Processing Workshops. 2005, p. 273-281 9 p., 1488705.

Research output: Contribution to journalConference article

13 Citations (Scopus)

Pipeline scheduling with input port constraints for an FPGA-based biochemical simulator

Ishimori, T., Yamada, H., Shibata, Y., Osana, Y., Yoshimi, M., Nishikawa, Y., Amano, H., Funahashi, A., Hiroi, N. & Oguri, K., 2009 Jun 22, In : Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 5453, p. 368-373 6 p.

Research output: Contribution to journalConference article

3 Citations (Scopus)

Reconfigurable Markov chain simulator for analysis of parallel systems

Yamamoto, O., Shibata, Y., Kurosawa, H. & Amano, H., 1997 Dec 1, In : Proceedings of the Annual IEEE International Conference on Innovative Systems in Silicon. p. 107-116 10 p.

Research output: Contribution to journalConference article

2 Citations (Scopus)
6 Citations (Scopus)
Conference contribution

(SM)**2 -II: A NEW VERSION OF THE SPARSE MATRIX SOLVING MACHINE.

Amano, H., Boku, T., Kudoh, T. & Aiso, H., 1985 Dec 1, Conference Proceedings - Annual Symposium on Computer Architecture. IEEE, p. 100-107 8 p. (Conference Proceedings - Annual Symposium on Computer Architecture).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Citations (Scopus)

(SM)2: SPARSE MATRIX SOLVING MACHINE.

Amano, H., Yoshida, T. & Aiso, H., 1983, Conference Proceedings - Annual Symposium on Computer Architecture. IEEE, p. 213-220 8 p. (Conference Proceedings - Annual Symposium on Computer Architecture).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

3D layout of spidergon, flattened butterfly and dragonfly on a chip stack with inductive coupling through chip interface

Nakahara, H., Yasudo, R., Matsutani, H., Amano, H. & Koibuchi, M., 2017 Nov 27, Proceedings - 14th International Symposium on Pervasive Systems, Algorithms and Networks, I-SPAN 2017, 11th International Conference on Frontier of Computer Science and Technology, FCST 2017 and 3rd International Symposium of Creative Computing, ISCC 2017. Institute of Electrical and Electronics Engineers Inc., p. 52-59 8 p. (Proceedings - 14th International Symposium on Pervasive Systems, Algorithms and Networks, I-SPAN 2017, 11th International Conference on Frontier of Computer Science and Technology, FCST 2017 and 3rd International Symposium of Creative Computing, ISCC 2017; vol. 2017-November).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

3D Shared Bus Architecture Using Inductive Coupling Interconnect

Nomura, A., Fujita, Y., Matsutani, H. & Amano, H., 2015 Nov 11, Proceedings - IEEE 9th International Symposium on Embedded Multicore/Manycore SoCs, MCSoC 2015. Institute of Electrical and Electronics Engineers Inc., p. 259-266 8 p. 7328213

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7MOPS/lemon-battery image processing demonstration with an ultra-low power reconfigurable accelerator CMA-SOTB-2

Masuyama, K., Fujita, Y., Okuhara, H. & Amano, H., 2015 Oct 7, 25th International Conference on Field Programmable Logic and Applications, FPL 2015. Institute of Electrical and Electronics Engineers Inc., 7293964

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

A 0.8-μm BiCMOS sea-of-gates implementation of the tandem banyan fast packet switch

Chiussi, F. M., Amano, H. & Tobagi, F. A., 1991 Dec 1, Proceedings of the Custom Integrated Circuits Conference. Publ by IEEE, (Proceedings of the Custom Integrated Circuits Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

A 2.72GOPS/11mW low power reconfigurable accelerator with a highly parallel datapath consisting of combinatorial circuits in 65nm CMOS

Ozaki, N., Yasuda, Y., Saito, Y., Ikebuchi, D., Kimura, M., Amano, H., Nakamura, H., Usami, K., Namiki, M. & Kondo, M., 2011, 2011 International Symposium on Integrated Circuits, ISIC 2011. p. 579-584 6 p. 6131929. (2011 International Symposium on Integrated Circuits, ISIC 2011).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A 297mops/0.4mw ultra low power coarse-grained reconfigurable accelerator CMA-SOTB-2

Masuyama, K., Fujita, Y., Okuhara, H. & Amano, H., 2016 Jan 25, 2015 International Conference on ReConFigurable Computing and FPGAs, ReConFig 2015. Institute of Electrical and Electronics Engineers Inc., 7393280

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

A case for random shortcut topologies for HPC interconnects

Koibuchi, M., Matsutani, H., Amano, H., Hsu, D. F. & Casanova, H., 2012 Aug 15, 2012 39th Annual International Symposium on Computer Architecture, ISCA 2012. p. 177-188 12 p. 6237016. (Proceedings - International Symposium on Computer Architecture).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

83 Citations (Scopus)

A Case for Uni-directional Network Topologies in Large-Scale Clusters

Koibuchi, M., Totoki, T., Matsutani, H., Amano, H., Chaix, F., Fujiwara, I. & Casanova, H., 2017 Sep 22, Proceedings - 2017 IEEE International Conference on Cluster Computing, CLUSTER 2017. Institute of Electrical and Electronics Engineers Inc., Vol. 2017-September. p. 178-187 10 p. 8048929

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

A case for wireless 3D NoCs for CMPs

Matsutani, H., Bogdan, P., Marculescu, R., Take, Y., Sasaki, D., Zhang, H., Koibuchi, M., Kuroda, T. & Amano, H., 2013 May 20, 2013 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013. p. 23-28 6 p. 6509553. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

36 Citations (Scopus)

Accelerating Deep Learning using Multiple GPUs and FPGA-Based 10GbE Switch

Itsubo, T., Koibuchi, M., Amano, H. & Matsutani, H., 2020 Mar, Proceedings - 2020 28th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2020. Institute of Electrical and Electronics Engineers Inc., p. 102-109 8 p. 9092145. (Proceedings - 2020 28th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2020).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Acceleration of ART Algorithm on an FPGA Board with Xilinx SDAccel

Okamoto, Y. & Amano, H., 2019 Nov, Proceedings - 2019 7th International Symposium on Computing and Networking Workshops, CANDARW 2019. Institute of Electrical and Electronics Engineers Inc., p. 280-284 5 p. 8951517. (Proceedings - 2019 7th International Symposium on Computing and Networking Workshops, CANDARW 2019).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Acceleration of deep recurrent neural networks with an FPGA cluster

Sun, Y., Ben Ahmed, A. & Amano, H., 2019 Jun 6, Proceedings of the 10th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, HEART 2019. Association for Computing Machinery, 18. (ACM International Conference Proceeding Series).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Acceleration of Full-PIC Simulation on a CPU-FPGA Tightly Coupled Environment

Sakai, R., Sugimoto, N., Amano, H., Miyajima, T. & Fujita, N., 2016 Dec 5, Proceedings - IEEE 10th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2016. Institute of Electrical and Electronics Engineers Inc., p. 8-14 7 p. 7774414

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Acceleration of the aggregation process in a Hall-thruster simulation using Intel FPGA SDK for OpenCL

Noda, H., Sakai, R., Miyajima, T., Fujita, N. & Amano, H., 2017 Jun 7, Proceedings of the 8th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, HEART 2017. Association for Computing Machinery, 20

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Accelerator-in-switch: A framework for tightly coupled switching hub and an accelerator with FPGA

Tsuruta, C., Kaneda, T., Nishikawa, N. & Amano, H., 2017 Oct 2, 2017 27th International Conference on Field Programmable Logic and Applications, FPL 2017. Institute of Electrical and Electronics Engineers Inc., 8056846

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

A circuit division method for high-level synthesis on multi-FPGA systems

Daiki, K., Miyajima, T. & Amano, H., 2013 Aug 19, Proceedings - 27th International Conference on Advanced Information Networking and Applications Workshops, WAINA 2013. p. 156-161 6 p. 6550389. (Proceedings - 27th International Conference on Advanced Information Networking and Applications Workshops, WAINA 2013).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A coarse grained-reconfigurable accelerator with energy efficient MTJ-based non-volatile flip-flops

Ikezoe, T., Amano, H., Akaike, J., Usami, K., Kudo, M., Hiraga, K., Shuto, Y. & Yagami, K., 2019 Feb 13, 2018 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2018. Andrews, D., Feregrino, C., Cumplido, R. & Stroobandt, D. (eds.). Institute of Electrical and Electronics Engineers Inc., 8641712. (2018 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2018).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

A coarse-grained reconfigurable architecture with a fault tolerant non-volatile configurable memory

Ikezoe, T., Kojima, T. & Amano, H., 2019 Dec, Proceedings - 2019 International Conference on Field-Programmable Technology, ICFPT 2019. Institute of Electrical and Electronics Engineers Inc., p. 81-89 9 p. 8977850. (Proceedings - 2019 International Conference on Field-Programmable Technology, ICFPT 2019; vol. 2019-December).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A combining technique of rate law functions for a cost-effective reconfigurable biological simulator

Yamada, H., Iwanaga, N., Shibata, Y., Osana, Y., Yoshimi, M., Iwaoka, Y., Nishikawa, Y., Kojima, T., Amano, H., Funahashi, A., Hiroi, N., Hiroaki Kitano, K. & Kiyoshi Oguri, O., 2007 Dec 1, Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL. p. 808-811 4 p. 4380774. (Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

A configuration data multicasting method for coarse-grained reconfigurable architectures

Kojima, T. & Amano, H., 2018 Nov 9, Proceedings - 2018 International Conference on Field-Programmable Logic and Applications, FPL 2018. Institute of Electrical and Electronics Engineers Inc., p. 239-242 4 p. 8533501. (Proceedings - 2018 International Conference on Field-Programmable Logic and Applications, FPL 2018).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

A context dependent clock control mechanism for dynamically reconfigurable processors

Amano, H., Hasegawa, Y., Abe, S., Ishikawa, K., Tsutsumi, S., Kurotaki, S., Nakamura, T. & Nishimura, T., 2006 Dec 1, Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL. p. 575-580 6 p. 4101031. (Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

A Co-processor design of an energy efficient reconfigurable accelerator CMA

Izawa, M., Ozaki, N., Koizumi, Y., Uno, R. & Amano, H., 2013, Proceedings - 2013 1st International Symposium on Computing and Networking, CANDAR 2013. p. 148-154 7 p. 6726890. (Proceedings - 2013 1st International Symposium on Computing and Networking, CANDAR 2013).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

A cost-effective context memory structure for dynamically reconfigurable processors

Suzuki, M., Hasegawa, Y., Tuan, V. M., Abe, S. & Amano, H., 2006, 20th International Parallel and Distributed Processing Symposium, IPDPS 2006. IEEE Computer Society, 1639433. (20th International Parallel and Distributed Processing Symposium, IPDPS 2006; vol. 2006).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

ACRO: Assignment of channels in reverse order to make arbitrary routing deadlock-free

Kawano, R., Nakahara, H., Tade, S., Fujiwara, I., Matsutani, H., Koibuchi, M. & Amano, H., 2016 Aug 23, 2016 IEEE/ACIS 15th International Conference on Computer and Information Science, ICIS 2016 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 7550818

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Adaptive body bias control scheme for ultra low-power network-on-chip systems

Ben Ahmed, A., Okuhara, H., Matsutani, H., Koibuchi, M. & Amano, H., 2018 Nov 16, Proceedings - 2018 IEEE 12th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2018. Institute of Electrical and Electronics Engineers Inc., p. 146-153 8 p. 8540227

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Adaptive power gating for function units in a microprocessor

Usami, K., Hashida, T., Koyama, S., Yamamoto, T., Ikebuchi, D., Amano, H., Namiki, M., Kondo, M. & Nakamura, H., 2010 May 28, Proceedings of the 11th International Symposium on Quality Electronic Design, ISQED 2010. p. 29-37 9 p. 5450407. (Proceedings of the 11th International Symposium on Quality Electronic Design, ISQED 2010).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Adaptive routing on the recursive diagonal torus

Funahashi, A., Hanawa, T., Kudoh, T. & Amano, H., 1997, Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Springer Verlag, Vol. 1336. p. 171-182 12 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 1336).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

A datapath classification method for FPGA-based scientific application accelerator systems

Ogawa, Y., Ooya, T., Osana, Y., Yoshimi, M., Nishikawa, Y., Funahashi, A., Hiroi, N., Amano, H., Shibata, Y. & Oguri, K., 2010 Dec 1, Proceedings - 2010 International Conference on Field-Programmable Technology, FPT'10. p. 441-444 4 p. 5681455. (Proceedings - 2010 International Conference on Field-Programmable Technology, FPT'10).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Adding slow-silent virtual channels for low-power on-chip networks

Matsutani, H., Koibuchi, M., Wang, D. & Amano, H., 2008 May 28, Proceedings - Second IEEE International Symposium on Networks-on-Chip, NOCS 2008. p. 23-32 10 p. 4492722. (Proceedings - Second IEEE International Symposium on Networks-on-Chip, NOCS 2008).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

33 Citations (Scopus)