• 2598 Citations
  • 23 h-Index
1983 …2020

Research output per year

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Research Output

Conference contribution

Performance analysis for the arbitor of IEEE standard backplane bus Futurebus/Futurebus+

Yamamoto, O., Takemoto, T., Kimura, T. & Amano, H., 1993 Jan 1, Proc IEEE 1993 Pac Rim Conf Commun Comput Signal Process. Publ by IEEE, p. 386-389 4 p. (Proc IEEE 1993 Pac Rim Conf Commun Comput Signal Process).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Performance analysis of clearspeed's CSX600 interconnects

Nishikawa, Y., Koibuchi, M., Yoshimi, M., Shitara, A., Miura, K. & Amano, H., 2009 Nov 19, Proceedings - 2009 IEEE International Symposium on Parallel and Distributed Processing with Applications, ISPA 2009. p. 203-210 8 p. 5207934. (Proceedings - 2009 IEEE International Symposium on Parallel and Distributed Processing with Applications, ISPA 2009).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Performance analysis of fully-adaptable CRC accelerators on an FPGA

Akagic, A. & Amano, H., 2012 Dec 12, Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012. p. 575-578 4 p. 6339374. (Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Performance and cost analysis of time-multiplexed execution on the dynamically reconfigurable processor

Amano, H., Abe, S., Hasegawa, Y., Deguchi, K. & Suzuki, M., 2005 Dec 1, Proceedings - 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2005. p. 315-316 2 p. 1508569. (Proceedings - 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2005; vol. 2005).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Performance and power analysis of time-multiplexed execution on dynamically reconfigurable processor

Hasegawa, Y., Abe, S., Kurotaki, S., Tuan, V. M., Katsura, N., Nakamura, T., Nishimura, T. & Amano, H., 2006 Jan 1, 20th International Parallel and Distributed Processing Symposium, IPDPS 2006. IEEE Computer Society, 1639431. (20th International Parallel and Distributed Processing Symposium, IPDPS 2006; vol. 2006).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Performance Estimation for Exascale Reconfigurable Dataflow Platforms

Yasudo, R., Coutinho, J., Varbanescu, A., Luk, W., Amano, H. & Becker, T., 2018 Dec, Proceedings - 2018 International Conference on Field-Programmable Technology, FPT 2018. Institute of Electrical and Electronics Engineers Inc., p. 317-320 4 p. 8742283. (Proceedings - 2018 International Conference on Field-Programmable Technology, FPT 2018).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Performance evaluation of 3-dimensional MIN with cache consistency maintenance mechanism

Tanabe, Y., Midorikawa, T., Shiraishi, D., Shigeno, M., Hanawa, T. & Amano, H., 2003 Dec 1, Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA 2003. Arabnia, H. R., Mun, Y., Arabnia, H. R. & Mun, Y. (eds.). p. 1148-1154 7 p. (Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications; vol. 3).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Performance evaluation of an FPGA-based biochemical simulator ReCSiP

Osana, Y., Yoshimi, M., Iwaoka, Y., Kojima, T., Nishikawa, Y., Funahashi, A., Hiroi, N., Kitano, H., Amano, H., Shibata, Y. & Iwanaga, N., 2006 Dec 1, Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL. p. 845-850 6 p. 4101089. (Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Performance Evaluation of a Prototype of RHiNET-2: A Network-based Distributed Parallel Computing System

Otsuka, T., Watanabe, K., Tsuchiya, J. I., Harada, H., Yamamoto, J., Nishi, H., Kudoh, T. & Amano, H., 2003 Dec 1, 21st IASTED International Multi-Conference on Applied Informatics. p. 738-743 6 p. (IASTED International Multi-Conference on Applied Informatics; vol. 21).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Performance evaluation of instruction set architecture of MBP-light: A distributed memory controller for a large scale multiprocessor

Suzuki, N. & Amano, H., 2003 Dec 1, Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA 2003. Arabnia, H. R., Mun, Y., Arabnia, H. R. & Mun, Y. (eds.). p. 1155-1161 7 p. (Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications; vol. 3).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Performance evaluation of multiple lookup tables algorithms for generating CRC on an FPGA

Akagić, A. & Amano, H., 2011 Aug 23, Proceedings of 2011 1st International Symposium on Access Spaces, ISAS 2011. p. 164-169 6 p. 5960941. (Proceedings of 2011 1st International Symposium on Access Spaces, ISAS 2011).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Performance Evaluation of PEACH3: Field-Programmable Gate Array Switch for Tightly Coupled Accelerators

Kaneda, T., Sakai, R., Nishikawa, N., Hanawa, T., Tsuruta, C. & Amano, H., 2017 Jun 7, Proceedings of the 8th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, HEART 2017. Association for Computing Machinery, 9

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Performance evaluation of power-aware multi-tree ethernet for HPC interconnects

Koibuchi, M., Watanabe, T., Minamihata, A., Nakao, M., Hiroyasu, T., Matsutani, H. & Amano, H., 2011 Dec 1, Proceedings - 2011 2nd International Conference on Networking and Computing, ICNC 2011. p. 50-57 8 p. 6131793. (Proceedings - 2011 2nd International Conference on Networking and Computing, ICNC 2011).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Performance evaluation of RHiNET 2/NI: A network interface for distributed parallel computing systems

Watanabe, K., Otsuka, T., Tsuchiya, J. I., Amano, H., Harada, H., Yamamoto, J., Nishi, H. & Kudoh, T., 2003 Dec 1, Proceedings - CCGrid 2003: 3rd IEEE/ACM International Symposium on Cluster Computing and the Grid. p. 318-325 8 p. 1199383. (Proceedings - CCGrid 2003: 3rd IEEE/ACM International Symposium on Cluster Computing and the Grid).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Citations (Scopus)

Performance evaluation of routing algorithms in RHiNET-2 cluster

Koibuchi, M., Watanabe, K., Kono, K., Jouraku, A. & Amano, H., 2003 Jan 1, Proceedings - IEEE International Conference on Cluster Computing, CLUSTER 2003. Institute of Electrical and Electronics Engineers Inc., p. 395-402 8 p. 1253339. (Proceedings - IEEE International Conference on Cluster Computing, ICCC; vol. 2003-January).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Citations (Scopus)

Performance evaluation of WASMII: A data driven computer on a virtual hardware

Ling, X. P. & Amano, H., 1993 Jan 1, PARLE 1993 - Parallel Architectures and Languages Europe - 5th International PARLE Conference, Proceedings. Bode, A., Reeve, M. & Wolf, G. (eds.). Springer Verlag, p. 610-621 12 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 694 LNCS).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Performance evaluation on low-latency communication mechanism of DIMMnet-2

Kitamura, A., Miyabe, Y., Miyashiro, T., Tanabe, N., Nakajo, H. & Amano, H., 2007 Dec 1, Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2007. p. 57-62 6 p. (Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Systems).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Performance improvement methodology for ClearSpeed's CSX600

Nishikawa, Y., Koibuchi, M., Yoshimi, M., Miura, K. & Amano, H., 2007 Dec 1, 2007 International Conference on Parallel Processing, ICPP. 4343884. (Proceedings of the International Conference on Parallel Processing).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Performance Prediction for Large-Scale Heterogeneous Platforms

Yasudo, R., Varbanescu, A. L., Coutinho, J. G. F., Luk, W. & Amano, H., 2018 Sep 7, Proceedings - 26th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2018. Institute of Electrical and Electronics Engineers Inc., 1 p. 8457669

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Power centric application mapping for dynamically reconfigurable processor array with Dual Vdd and Dual Vth

Hironaka, K. & Amano, H., 2011 Dec 1, Proceedings - 2011 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2011. p. 404-409 6 p. 6128611. (Proceedings - 2011 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2011).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Power Optimization Considering the Chip Temperature of Low Power Reconfigurable Accelerator CMA-SOTB

Fujita, Y., Okuhara, H., Masuyama, K. & Amano, H., 2016 Mar 2, Proceedings - 2015 3rd International Symposium on Computing and Networking, CANDAR 2015. Institute of Electrical and Electronics Engineers Inc., p. 21-29 9 p. 7424265

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Power reduction techniques for dynamically reconfigurable processor arrays

Nishimura, T., Hirai, K., Saito, Y., Nakamura, T., Hasegawa, Y., Tsutsusmi, S., Tunbunheng, V. & Amano, H., 2008 Nov 3, Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL. p. 305-310 6 p. 4629949. (Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

17 Citations (Scopus)

Practical implementation of a network-based Stochastic biochemical simulation system on an FPGA

Yoshimi, M., Nishikawa, Y., Osana, Y., Funahashi, A., Hiroi, N., Shibata, Y., Yamada, H., Kitano, H. & Amano, H., 2008 Nov 3, Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL. p. 663-666 4 p. 4630034. (Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Prediction router: Yet another low latency on-chip router architecture

Matsutani, H., Koibuchi, M., Amano, H. & Yoshinaga, T., 2009 Apr 24, Proceedings - 15th International Symposium on High-Performance Computer Architecture, HPCA - 15 2009. p. 367-378 12 p. 4798274. (Proceedings - International Symposium on High-Performance Computer Architecture).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

60 Citations (Scopus)

Preliminary evaluation of batch-learning self-organizing map algorithm on a graphic processor

Shitara, A., Nishikawa, Y., Yoshimi, M., Abe, T., Ikemura, T. & Amano, H., 2010, Proceedings of the 9th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2010. Acta Press, p. 96-104 9 p. (Proceedings of the 9th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2010).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Preliminary evaluations of a FPGA-based-prototype of DIMMnet-2 network interface

Tanabe, N., Kitamura, A., Miyashiro, T., Miyabe, Y., Izawa, T., Hamada, Y., Nakajo, H. & Amano, H., 2005, IWIA 2005: Innovative Architecture for Future Generation High-Performance Processors and Systems. IEEE Computer Society, p. 9-17 9 p. 1587833. (Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems; vol. 2005).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Citations (Scopus)

Proposal of auto MPI expansion tool for cell broadband engine cluster

Nakahama, T., Yamada, M., Yoshimi, M. & Amano, H., 2011, Proceedings - 2011 2nd International Conference on Networking and Computing, ICNC 2011. p. 166-172 7 p. 6131802. (Proceedings - 2011 2nd International Conference on Networking and Computing, ICNC 2011).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Prototyping on using a DIMM slot as a high-performance I/O interface

Tanabe, N., Hamada, Y., Mitsuhashi, A., Nakajo, H., Yamamoto, J., Imashiro, H., Kudoh, T. & Amano, H., 2003 Jan 1, Innovative Architecture for Future Generation High-Performance Processors and Systems, IWIA 2003. Veidenbaum, A. & Joe, K. (eds.). IEEE Computer Society, p. 108-116 9 p. 1262788. (Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems; vol. 2003-January).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Randomizing Packet Memory Networks for Low-Latency Processor-Memory Communication

Fujiki, D., Matsutani, H., Koibuchi, M. & Amano, H., 2016 Mar 31, Proceedings - 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2016. Institute of Electrical and Electronics Engineers Inc., p. 168-175 8 p. 7445327

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Real chip evaluation of a low power CGRA with optimized application mapping

Kojima, T., Ando, N., Matshushita, Y., Okuhara, H., Doan, N. A. V. & Amano, H., 2018 Jun 20, Proceedings of the 9th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, HEART 2018. Association for Computing Machinery, a13

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Real chip performance evaluation on through chip interface IP for renesas SOTB 65nm process

Kayashima, H., Kojima, T., Okuhara, H., Shidei, T. & Amano, H., 2019 Nov, Proceedings - 2019 7th International Symposium on Computing and Networking Workshops, CANDARW 2019. Institute of Electrical and Electronics Engineers Inc., p. 269-274 6 p. 8951550. (Proceedings - 2019 7th International Symposium on Computing and Networking Workshops, CANDARW 2019).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Reconfigurable out-of-order mechanism generator for unstructured grid computation in computational fluid dynamics

Akamine, T., Inakagata, K., Osana, Y., Fujita, N. & Amano, H., 2012 Dec 12, Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012. p. 136-142 7 p. 6339277. (Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Reconfigurable systems: New activities in asia

Amano, H., Shibata, Y. & Uno, M., 2000 Jan 1, Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing - 10th International Conference, FPL 2000, Proceedings. Hartenstein, R. W. & Grunbacher, H. (eds.). Springer Verlag, p. 585-594 10 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 1896).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Recursive diagonal torus: An interconnection network for massively parallel computers

Yang, Y. L., Amano, H., Shibamura, H. & Sueyoshi, T., 1993 Dec 1, Proceedings of the 5th IEEE Symposium on Parallel and Distributed Processing. Anon (ed.). Publ by IEEE, p. 591-594 4 p. (Proceedings of the 5th IEEE Symposium on Parallel and Distributed Processing).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

11 Citations (Scopus)

Reducing instruction TLB's leakage power consumption for embedded processors

Lei, Z., Xu, H., Ikebuchi, D., Amano, H., Sunata, T. & Namiki, M., 2010 Nov 24, 2010 International Conference on Green Computing, Green Comp 2010. p. 477-484 8 p. 5598277. (2010 International Conference on Green Computing, Green Comp 2010).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Reducing power consumption for dynamically reconfigurable processor array with partially fixed configuration mapping

Hironaka, K., Kimura, M., Saito, Y., Sano, T., Kato, M., Tunbunheng, V., Yasuda, Y. & Amano, H., 2010 Dec 1, Proceedings - 2010 International Conference on Field-Programmable Technology, FPT'10. p. 349-352 4 p. 5681431. (Proceedings - 2010 International Conference on Field-Programmable Technology, FPT'10).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Reducing power for dynamically reconfigurable processor array by reducing number of reconfigurations

Kimura, M., Hironaka, K. & Amano, H., 2011 Dec 1, 2011 International Conference on Field-Programmable Technology, FPT 2011. 6132707. (2011 International Conference on Field-Programmable Technology, FPT 2011).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Reduction calculator in an FPGA based switching Hub for high performance clusters

Kuhara, T., Tsuruta, C., Hanawa, T. & Amano, H., 2015 Oct 7, 25th International Conference on Field Programmable Logic and Applications, FPL 2015. Institute of Electrical and Electronics Engineers Inc., 7293985

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Research of PE array connection network for cool mega-array

Uno, R., Ozaki, N. & Amano, H., 2013 Aug 19, Proceedings - 27th International Conference on Advanced Information Networking and Applications Workshops, WAINA 2013. p. 144-149 6 p. 6550387. (Proceedings - 27th International Conference on Advanced Information Networking and Applications Workshops, WAINA 2013).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

RHiNET/NI: A reconfigurable network interface for cluster computing

Izu, N., Yokoyama, T., Tsuchiya, J., Watanabe, K. & Amano, H., 2002, Field-Programmable Logic and Applications: Reconfigurable Computing is Going Mainstream - 12th International Conference, FPL 2002, Proceedings. Springer Verlag, p. 1118-1121 4 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 2438 LNCS).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

RHiNET-3/SW: An 80-Gbit/s high-speed network switch for distributed parallel computing

Nishimura, S., Kudoh, T., Nishi, H., Yamamoto, J., Ueno, R., Harasawa, K., Fukuda, S., Shikichi, Y., Akutsu, S., Tasho, K. & Amano, H., 2001 Jan 1, HOT Interconnects 9, HIS 2001. Institute of Electrical and Electronics Engineers Inc., p. 119-123 5 p. 946703. (Proceedings - Symposium on the High Performance Interconnects, Hot Interconnects; vol. 2001-January).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

RHiNET A network for high performance parallel computing using locally distributed computers

Kudoh, T., Nishimura, S., Yamamoto, J., Nishi, H., Tatebe, O. & Amano, H., 1999 Jan 1, Innovative Architecture for Future Generation High-Performance Processors and Systems - 1999 International Workshop on Innovative Architectures, IWIA 1999. Nakashima, H. & Veidenbaum, A. (eds.). IEEE Computer Society, p. 69-73 5 p. 898844. (Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems; vol. 1999-November).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

18 Citations (Scopus)

RoMultiC: Fast and simple configuration data multicasting scheme for coarse grain reconfigurable devices

Tunbunheng, V., Suzuki, M. & Amano, H., 2005 Dec 1, Proceedings - 2005 IEEE International Conference on Field Programmable Technology. p. 129-136 8 p. 1568536. (Proceedings - 2005 IEEE International Conference on Field Programmable Technology; vol. 2005).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

38 Citations (Scopus)

Routing algorithms based on 2D turn model for irregular networks

Jouraku, A., Koibuchi, M., Amano, H. & Funahashi, A., 2002 Jan 1, Proceedings - International Symposium on Parallel Architectures, Algorithms and Networks, I-SPAN 2002. Hsu, D. F., Saldana, R. P. & Ibarra, O. H. (eds.). IEEE Computer Society, p. 289-294 6 p. 1004296. (Proceedings of the International Symposium on Parallel Architectures, Algorithms and Networks, I-SPAN; vol. 2002-January).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

13 Citations (Scopus)

RSM (RECEIVER SELECTABLE MULTICAST): A COMMUNICATION MECHANISM FOR MULTIPROCESSORS.

Amano, H., 1987 Jan 1, Unknown Host Publication Title. IEEE, p. 149-156 8 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Run-time power gating of on-chip routers using look-ahead routing

Matsutani, H., Koibuchi, M., Amano, H. & Wang, D., 2008 Aug 21, 2008 Asia and South Pacific Design Automation Conference, ASP-DAC. p. 55-60 6 p. 4484015. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

67 Citations (Scopus)

Scalable deep neural network accelerator cores with cubic integration using through chip interface

Sakamoto, R., Takata, R., Ishii, J., Kondo, M., Nakamura, H., Ohkubo, T., Kojima, T. & Amano, H., 2018 May 29, Proceedings - International SoC Design Conference 2017, ISOCC 2017. Institute of Electrical and Electronics Engineers Inc., p. 155-156 2 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Shared vs. Snoop: Evaluation of cache structure for single-chip multiprocessors

Kisuki, T., Wakabayashi, M., Yamamoto, J., Inoue, K. & Amano, H., 1997 Jan 1, Euro-Par 1997 Parallel Processing - Third International Conference, Proceedings. Springer Verlag, p. 793-797 5 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 1300 LNCS).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Significant papers from the first 25 years of the FPL conference

Leong, P. H. W., Amano, H., Anderson, J., Bertels, K., Cardoso, J. M. P., Diessel, O., Gogniat, G., Hutton, M., Lee, J., Luk, W., Lysaght, P., Platzner, M., Prasanna, V. K., Rissa, T., Silvano, C., So, H. & Wang, Y., 2015 Oct 7, 25th International Conference on Field Programmable Logic and Applications, FPL 2015. Institute of Electrical and Electronics Engineers Inc., 7293747. (25th International Conference on Field Programmable Logic and Applications, FPL 2015).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

SLD-1(Silent Large Datapath): A ultra low power reconfigurable accelerator

Ozaki, N., Usami, K., Amano, H., Namiki, M., Nakamura, H. & Kondo, M., 2011, IEEE Symposium on Low-Power and High-Speed Chips - 2011 IEEE COOL Chips XIV, Proceedings. 5890918. (IEEE Symposium on Low-Power and High-Speed Chips - 2011 IEEE COOL Chips XIV, Proceedings).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)