• 2598 Citations
  • 23 h-Index
1983 …2020

Research output per year

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Research Output

Paper

A hardware complete detection mechanism for an energy efficient reconfigurable accelerator CMA

Tsusaka, A., Izawa, M., Uno, R., Ozaki, N. & Amano, H., 2013 Jan 1.

Research output: Contribution to conferencePaper

1 Citation (Scopus)

A new memory module for COTS-based personal supercomputing

Tanabe, N., Nakatake, M., Hakozaki, H., Dohi, Y., Nakajo, H. & Amano, H., 2004 Dec 1, p. 40-48. 9 p.

Research output: Contribution to conferencePaper

11 Citations (Scopus)

An OpenCL runtime library for embedded multi-core accelerator

Sakamoto, R., Sato, M., Koizumi, Y., Amano, H. & Namiki, M., 2012 Nov 19, p. 419-422. 4 p.

Research output: Contribution to conferencePaper

1 Citation (Scopus)

Demonstration of a heterogeneous multi-core processor with 3-D inductive coupling links

Koizumi, Y., Miura, N., Take, Y., Matsutani, H., Kuroda, T., Amano, H., Sakamoto, R., Namiki, M., Usami, K., Kondo, M. & Nakamura, H., 2013 Jan 1.

Research output: Contribution to conferencePaper

Distributed shared memory architecture for JUMP-1: A general-purpose MPP prototype

Matsumoto, T., Kudoh, T., Nishimura, K., Hiraki, K., Amano, H. & Tanaka, H., 1996 Jan 1, p. 131-137. 7 p.

Research output: Contribution to conferencePaper

5 Citations (Scopus)

Fine-grained power control using a multi-voltage variable pipeline router

Nakamura, T., Matsutani, H., Koibuchi, M., Usami, K. & Amano, H., 2012 Dec 1, p. 59-66. 8 p.

Research output: Contribution to conferencePaper

4 Citations (Scopus)

LSI implementation of the simple serial synchronized multistage interconnection network

Kamei, T., Sasahara, M. & Amano, H., 1997 Jan 1, p. 673-674. 2 p.

Research output: Contribution to conferencePaper

1 Citation (Scopus)

Memory based light weight communication architecture for local area distributed computing

Kudoh, T., Yamamoto, J., Sudoh, F., Amano, H., Ishikawa, Y. & Sato, M., 1997 Dec 1, p. 133-139. 7 p.

Research output: Contribution to conferencePaper

5 Citations (Scopus)

Message transfer algorithms on the recursive diagonal torus

Yang, Y. & Amano, H., 1994 Dec 1, p. 310-317. 8 p.

Research output: Contribution to conferencePaper

4 Citations (Scopus)

MINC (Multistage Interconnection Network with Cache control mechanism) chip

Midorikawa, T., Kamei, T., Hanawa, T. & Amano, H., 1998 Dec 1, p. 337-338. 2 p.

Research output: Contribution to conferencePaper

2 Citations (Scopus)

Overview of the JUMP-1, an MPP prototype for general-purpose parallel computations

Hiraki, K., Amano, H., Kuga, M., Sueyoshi, T., Kudoh, T., Nakashima, H., Nakajo, H., Matsuda, H., Matsumoto, T. & Mori, S. I., 1994 Dec 1, p. 427-434. 8 p.

Research output: Contribution to conferencePaper

10 Citations (Scopus)

RDT network router chip

Nishi, H., Amano, H., Nishimura, K., Anjo, K. I. & Kudoh, T., 1997 Jan 1, p. 675-676. 2 p.

Research output: Contribution to conferencePaper

Reconfigurable systems: Activities in Asia and South Pacific

Amano, H. & Shibata, Y., 1998 Dec 1, p. 453-457. 5 p.

Research output: Contribution to conferencePaper

4 Citations (Scopus)

ReCSiP: A ReConfigurable cell simulation platform - Accelerating biological applications with FPGA

Osana, Y., Fukushima, T. & Amano, H., 2004 Jun 1, p. 731-733. 3 p.

Research output: Contribution to conferencePaper

5 Citations (Scopus)

Removing context memory from a multi-context dynamically reconfigurable processor

Amano, H., Kimura, M. & Ozaki, N., 2012 Dec 1, p. 92-99. 8 p.

Research output: Contribution to conferencePaper

6 Citations (Scopus)

Rolling mapping/mesh: a mapping method/interconnection structure for a mesh with various densities

Murata, A. & Amano, H., 1995 Jan 1, p. 445-450. 6 p.

Research output: Contribution to conferencePaper

Task level pipelining on multiple accelerators via FPGA switch

Miyajima, T., Kuhara, T., Hanawa, T., Amano, H. & Boku, T., 2014 Jan 1, p. 267-274. 8 p.

Research output: Contribution to conferencePaper

Time-multiplexed execution on the dynamically reconfigurable processor - A performance/cost evaluation

Hasegawa, Y., Abe, S., Deguchi, K., Suzuki, M. & Amano, H., 2005 Jun 20. 1 p.

Research output: Contribution to conferencePaper

Towards the realistic `virtual hardware'

Shibata, Y., Miyazaki, H., Ling, X. P. & Amano, H., 1997 Dec 1, p. 50-55. 6 p.

Research output: Contribution to conferencePaper

Wavelength division multiple access ring: Virtual topology on a simple ring network

Dong, X., Kudoh, T. & Amano, H., 1997 Jan 1, p. 30-36. 7 p.

Research output: Contribution to conferencePaper

1 Citation (Scopus)
Review article

An FPGA-based acceleration method for metabolic simulation

Osana, Y., Fukushima, T., Yoshimi, M. & Amano, H., 2004 Aug, In : IEICE Transactions on Information and Systems. E87-D, 8, p. 2029-2037 9 p.

Research output: Contribution to journalReview article

4 Citations (Scopus)

A survey on dynamically reconfigurable processors

Amano, H., 2006 Dec, In : IEICE Transactions on Communications. E89-B, 12, p. 3179-3187 9 p.

Research output: Contribution to journalReview article

54 Citations (Scopus)

Optical network technologies for HPC: Computer-architects point of view

Koibuchi, M., Fujiwara, I., Ishii, K., Namiki, S., Chaix, F., Matsutani, H., Amano, H. & Kudoh, T., 2016 Mar 25, In : IEICE Electronics Express. 13, 6, 20152007.

Research output: Contribution to journalReview article

14 Citations (Scopus)