• 2598 Citations
  • 23 h-Index
1983 …2020

Research output per year

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Research Output

Review article

An FPGA-based acceleration method for metabolic simulation

Osana, Y., Fukushima, T., Yoshimi, M. & Amano, H., 2004 Aug, In : IEICE Transactions on Information and Systems. E87-D, 8, p. 2029-2037 9 p.

Research output: Contribution to journalReview article

4 Citations (Scopus)

A survey on dynamically reconfigurable processors

Amano, H., 2006 Dec, In : IEICE Transactions on Communications. E89-B, 12, p. 3179-3187 9 p.

Research output: Contribution to journalReview article

54 Citations (Scopus)

Optical network technologies for HPC: Computer-architects point of view

Koibuchi, M., Fujiwara, I., Ishii, K., Namiki, S., Chaix, F., Matsutani, H., Amano, H. & Kudoh, T., 2016 Mar 25, In : IEICE Electronics Express. 13, 6, 20152007.

Research output: Contribution to journalReview article

14 Citations (Scopus)
Paper

A fully pipelined FPGA architecture for stochastic simulation of chemical systems

Thomas, D. B. & Amano, H., 2013.

Research output: Contribution to conferencePaper

4 Citations (Scopus)

A hardware complete detection mechanism for an energy efficient reconfigurable accelerator CMA

Tsusaka, A., Izawa, M., Uno, R., Ozaki, N. & Amano, H., 2013 Jan 1.

Research output: Contribution to conferencePaper

1 Citation (Scopus)

A new memory module for COTS-based personal supercomputing

Tanabe, N., Nakatake, M., Hakozaki, H., Dohi, Y., Nakajo, H. & Amano, H., 2004 Dec 1, p. 40-48. 9 p.

Research output: Contribution to conferencePaper

11 Citations (Scopus)

An OpenCL runtime library for embedded multi-core accelerator

Sakamoto, R., Sato, M., Koizumi, Y., Amano, H. & Namiki, M., 2012 Nov 19, p. 419-422. 4 p.

Research output: Contribution to conferencePaper

1 Citation (Scopus)

Demonstration of a heterogeneous multi-core processor with 3-D inductive coupling links

Koizumi, Y., Miura, N., Take, Y., Matsutani, H., Kuroda, T., Amano, H., Sakamoto, R., Namiki, M., Usami, K., Kondo, M. & Nakamura, H., 2013 Jan 1.

Research output: Contribution to conferencePaper

Distributed shared memory architecture for JUMP-1: A general-purpose MPP prototype

Matsumoto, T., Kudoh, T., Nishimura, K., Hiraki, K., Amano, H. & Tanaka, H., 1996 Jan 1, p. 131-137. 7 p.

Research output: Contribution to conferencePaper

5 Citations (Scopus)

Fine-grained power control using a multi-voltage variable pipeline router

Nakamura, T., Matsutani, H., Koibuchi, M., Usami, K. & Amano, H., 2012 Dec 1, p. 59-66. 8 p.

Research output: Contribution to conferencePaper

4 Citations (Scopus)

LSI implementation of the simple serial synchronized multistage interconnection network

Kamei, T., Sasahara, M. & Amano, H., 1997 Jan 1, p. 673-674. 2 p.

Research output: Contribution to conferencePaper

1 Citation (Scopus)

Memory based light weight communication architecture for local area distributed computing

Kudoh, T., Yamamoto, J., Sudoh, F., Amano, H., Ishikawa, Y. & Sato, M., 1997 Dec 1, p. 133-139. 7 p.

Research output: Contribution to conferencePaper

5 Citations (Scopus)

Message transfer algorithms on the recursive diagonal torus

Yang, Y. & Amano, H., 1994 Dec 1, p. 310-317. 8 p.

Research output: Contribution to conferencePaper

4 Citations (Scopus)

MINC (Multistage Interconnection Network with Cache control mechanism) chip

Midorikawa, T., Kamei, T., Hanawa, T. & Amano, H., 1998 Dec 1, p. 337-338. 2 p.

Research output: Contribution to conferencePaper

2 Citations (Scopus)

Overview of the JUMP-1, an MPP prototype for general-purpose parallel computations

Hiraki, K., Amano, H., Kuga, M., Sueyoshi, T., Kudoh, T., Nakashima, H., Nakajo, H., Matsuda, H., Matsumoto, T. & Mori, S. I., 1994 Dec 1, p. 427-434. 8 p.

Research output: Contribution to conferencePaper

10 Citations (Scopus)

RDT network router chip

Nishi, H., Amano, H., Nishimura, K., Anjo, K. I. & Kudoh, T., 1997 Jan 1, p. 675-676. 2 p.

Research output: Contribution to conferencePaper

Reconfigurable systems: Activities in Asia and South Pacific

Amano, H. & Shibata, Y., 1998 Dec 1, p. 453-457. 5 p.

Research output: Contribution to conferencePaper

4 Citations (Scopus)

ReCSiP: A ReConfigurable cell simulation platform - Accelerating biological applications with FPGA

Osana, Y., Fukushima, T. & Amano, H., 2004 Jun 1, p. 731-733. 3 p.

Research output: Contribution to conferencePaper

5 Citations (Scopus)

Removing context memory from a multi-context dynamically reconfigurable processor

Amano, H., Kimura, M. & Ozaki, N., 2012 Dec 1, p. 92-99. 8 p.

Research output: Contribution to conferencePaper

6 Citations (Scopus)

Rolling mapping/mesh: a mapping method/interconnection structure for a mesh with various densities

Murata, A. & Amano, H., 1995 Jan 1, p. 445-450. 6 p.

Research output: Contribution to conferencePaper

Task level pipelining on multiple accelerators via FPGA switch

Miyajima, T., Kuhara, T., Hanawa, T., Amano, H. & Boku, T., 2014 Jan 1, p. 267-274. 8 p.

Research output: Contribution to conferencePaper

Time-multiplexed execution on the dynamically reconfigurable processor - A performance/cost evaluation

Hasegawa, Y., Abe, S., Deguchi, K., Suzuki, M. & Amano, H., 2005 Jun 20. 1 p.

Research output: Contribution to conferencePaper

Towards the realistic `virtual hardware'

Shibata, Y., Miyazaki, H., Ling, X. P. & Amano, H., 1997 Dec 1, p. 50-55. 6 p.

Research output: Contribution to conferencePaper

Wavelength division multiple access ring: Virtual topology on a simple ring network

Dong, X., Kudoh, T. & Amano, H., 1997 Jan 1, p. 30-36. 7 p.

Research output: Contribution to conferencePaper

1 Citation (Scopus)
Editorial

Guest editors' introduction ICFPT 2007

Amano, H. & Nakamura, T., 2009 Jun, In : ACM Transactions on Reconfigurable Technology and Systems. 2, 2, 7.

Research output: Contribution to journalEditorial

Message from the general chair and program co-chairs

Amano, H., Ha, Y. & Yamaguchi, Y., 2013 Dec 1, In : FPT 2013 - Proceedings of the 2013 International Conference on Field Programmable Technology. 6718314.

Research output: Contribution to journalEditorial

Message from the organizers

Amano, H., Nakamura, M., MacLoughlin, I. V., Yoshinaga, T., Fujita, S. & Nakano, K., 2012 Dec 1, In : Proceedings of the 2012 3rd International Conference on Networking and Computing, ICNC 2012. p. xi-xii 6424529.

Research output: Contribution to journalEditorial

Message from WReCS 2012 workshop co-chairs

Amano, H. & Uehara, M., 2012 Dec 14, In : Proceedings of the 2012 15th International Conference on Network-Based Information Systems, NBIS 2012. p. lxiv 6354991.

Research output: Contribution to journalEditorial

Special section on parallel and distributed computing and networking

Amano, H., 2012 Dec, In : IEICE Transactions on Information and Systems. E95-D, 12, 1 p.

Research output: Contribution to journalEditorial

Special section on parallel and distributed computing and networking

Amano, H., 2013 Dec, In : IEICE Transactions on Information and Systems. E96-D, 12, 1 p.

Research output: Contribution to journalEditorial

Special section on reconfigurable systems

Amano, H., 2012 Feb, In : IEICE Transactions on Information and Systems. E95-D, 2, 1 p.

Research output: Contribution to journalEditorial

Special section on reconfigurable systems

Amano, H., 2013 Jan 1, In : IEICE Transactions on Information and Systems. E96-D, 8, 1 p.

Research output: Contribution to journalEditorial

Conference contribution

(SM)**2 -II: A NEW VERSION OF THE SPARSE MATRIX SOLVING MACHINE.

Amano, H., Boku, T., Kudoh, T. & Aiso, H., 1985 Dec 1, Conference Proceedings - Annual Symposium on Computer Architecture. IEEE, p. 100-107 8 p. (Conference Proceedings - Annual Symposium on Computer Architecture).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Citations (Scopus)

(SM)2: SPARSE MATRIX SOLVING MACHINE.

Amano, H., Yoshida, T. & Aiso, H., 1983, Conference Proceedings - Annual Symposium on Computer Architecture. IEEE, p. 213-220 8 p. (Conference Proceedings - Annual Symposium on Computer Architecture).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

3D layout of spidergon, flattened butterfly and dragonfly on a chip stack with inductive coupling through chip interface

Nakahara, H., Yasudo, R., Matsutani, H., Amano, H. & Koibuchi, M., 2017 Nov 27, Proceedings - 14th International Symposium on Pervasive Systems, Algorithms and Networks, I-SPAN 2017, 11th International Conference on Frontier of Computer Science and Technology, FCST 2017 and 3rd International Symposium of Creative Computing, ISCC 2017. Institute of Electrical and Electronics Engineers Inc., p. 52-59 8 p. (Proceedings - 14th International Symposium on Pervasive Systems, Algorithms and Networks, I-SPAN 2017, 11th International Conference on Frontier of Computer Science and Technology, FCST 2017 and 3rd International Symposium of Creative Computing, ISCC 2017; vol. 2017-November).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

3D Shared Bus Architecture Using Inductive Coupling Interconnect

Nomura, A., Fujita, Y., Matsutani, H. & Amano, H., 2015 Nov 11, Proceedings - IEEE 9th International Symposium on Embedded Multicore/Manycore SoCs, MCSoC 2015. Institute of Electrical and Electronics Engineers Inc., p. 259-266 8 p. 7328213

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7MOPS/lemon-battery image processing demonstration with an ultra-low power reconfigurable accelerator CMA-SOTB-2

Masuyama, K., Fujita, Y., Okuhara, H. & Amano, H., 2015 Oct 7, 25th International Conference on Field Programmable Logic and Applications, FPL 2015. Institute of Electrical and Electronics Engineers Inc., 7293964

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

A 0.8-μm BiCMOS sea-of-gates implementation of the tandem banyan fast packet switch

Chiussi, F. M., Amano, H. & Tobagi, F. A., 1991 Dec 1, Proceedings of the Custom Integrated Circuits Conference. Publ by IEEE, (Proceedings of the Custom Integrated Circuits Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

A 2.72GOPS/11mW low power reconfigurable accelerator with a highly parallel datapath consisting of combinatorial circuits in 65nm CMOS

Ozaki, N., Yasuda, Y., Saito, Y., Ikebuchi, D., Kimura, M., Amano, H., Nakamura, H., Usami, K., Namiki, M. & Kondo, M., 2011, 2011 International Symposium on Integrated Circuits, ISIC 2011. p. 579-584 6 p. 6131929. (2011 International Symposium on Integrated Circuits, ISIC 2011).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A 297mops/0.4mw ultra low power coarse-grained reconfigurable accelerator CMA-SOTB-2

Masuyama, K., Fujita, Y., Okuhara, H. & Amano, H., 2016 Jan 25, 2015 International Conference on ReConFigurable Computing and FPGAs, ReConFig 2015. Institute of Electrical and Electronics Engineers Inc., 7393280

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

A case for random shortcut topologies for HPC interconnects

Koibuchi, M., Matsutani, H., Amano, H., Hsu, D. F. & Casanova, H., 2012 Aug 15, 2012 39th Annual International Symposium on Computer Architecture, ISCA 2012. p. 177-188 12 p. 6237016. (Proceedings - International Symposium on Computer Architecture).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

83 Citations (Scopus)

A Case for Uni-directional Network Topologies in Large-Scale Clusters

Koibuchi, M., Totoki, T., Matsutani, H., Amano, H., Chaix, F., Fujiwara, I. & Casanova, H., 2017 Sep 22, Proceedings - 2017 IEEE International Conference on Cluster Computing, CLUSTER 2017. Institute of Electrical and Electronics Engineers Inc., Vol. 2017-September. p. 178-187 10 p. 8048929

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

A case for wireless 3D NoCs for CMPs

Matsutani, H., Bogdan, P., Marculescu, R., Take, Y., Sasaki, D., Zhang, H., Koibuchi, M., Kuroda, T. & Amano, H., 2013 May 20, 2013 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013. p. 23-28 6 p. 6509553. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

36 Citations (Scopus)

Accelerating Deep Learning using Multiple GPUs and FPGA-Based 10GbE Switch

Itsubo, T., Koibuchi, M., Amano, H. & Matsutani, H., 2020 Mar, Proceedings - 2020 28th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2020. Institute of Electrical and Electronics Engineers Inc., p. 102-109 8 p. 9092145. (Proceedings - 2020 28th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2020).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Acceleration of ART Algorithm on an FPGA Board with Xilinx SDAccel

Okamoto, Y. & Amano, H., 2019 Nov, Proceedings - 2019 7th International Symposium on Computing and Networking Workshops, CANDARW 2019. Institute of Electrical and Electronics Engineers Inc., p. 280-284 5 p. 8951517. (Proceedings - 2019 7th International Symposium on Computing and Networking Workshops, CANDARW 2019).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Acceleration of deep recurrent neural networks with an FPGA cluster

Sun, Y., Ben Ahmed, A. & Amano, H., 2019 Jun 6, Proceedings of the 10th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, HEART 2019. Association for Computing Machinery, 18. (ACM International Conference Proceeding Series).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)