• 2531 Citations
  • 23 h-Index
1983 …2020

Research output per year

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Research Output

A performance evaluation of CUBE: One-dimensional 512 FPGA cluster

Yoshimi, M., Nishikawa, Y., Miki, M., Hiroyasu, T., Amano, H. & Mencer, O., 2010 Apr 29, Reconfigurable Computing: Architectures, Tools and Applications - 6th International Symposium, ARC 2010, Proceedings. p. 372-381 10 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 5992 LNCS).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

A performance evaluation of the multiprocessor testbed ATTEMPT-0

Terasawa, T., Yamamoto, O., Kudoh, T. & Amano, H., 1995 May, In : Parallel Computing. 21, 5, p. 701-730 30 p.

Research output: Contribution to journalArticle

2 Citations (Scopus)

A perpetuum mobile 32bit CPU on 65nm SOTB CMOS technology with reverse-body-bias assisted sleep mode

Kamohara, S., Sugii, N., Ishibashi, K., Usami, K., Amano, H., Kobayashi, K. & Pham, C. K., 2016 May 25, 2014 IEEE Hot Chips 26 Symposium, HCS 2014. Institute of Electrical and Electronics Engineers Inc., 7478838

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A perpetuum mobile 32bit CPU on 65nm SOTB CMOS technology with reverse-body-bias assisted sleep mode

Ishibashi, K., Sugii, N., Kamohara, S., Usami, K., Amano, H., Kobayashi, K. & Pham, C. K., 2015 Jul 1, In : IEICE Transactions on Electronics. E98C, 7, p. 536-543 8 p.

Research output: Contribution to journalArticle

17 Citations (Scopus)

A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14μA sleep current using Reverse Body Bias Assisted 65nm SOTB CMOS technology

Ishibashi, K., Sugii, N., Usami, K., Amano, H., Kobayashi, K., Pham, C. K., Makiyama, H., Yamamoto, Y., Shinohara, H., Iwamatsu, T., Yamaguchi, Y., Oda, H., Hasegawa, T., Okanishi, S., Yanagita, H., Kamohara, S., Kadoshima, M., Maekawa, K., Yamashita, T., Le, D. H. & 5 others, Yomogita, T., Kudo, M., Kitamori, K., Kondo, S. & Manzawa, Y., 2014 Jan 1, IEEE Symposium on Low-Power and High-Speed Chips - Proceedings for 2014 IEEE COOL Chips XVII. IEEE Computer Society, 6842954. (IEEE Symposium on Low-Power and High-Speed Chips - Proceedings for 2014 IEEE COOL Chips XVII).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

20 Citations (Scopus)

A port combination methodology for application-specific networks-on-chip on FPGAS

Wang, D., Matsutani, H., Koibuchi, M. & Amano, H., 2007 Dec, In : IEICE Transactions on Information and Systems. E90-D, 12, p. 1914-1922 9 p.

Research output: Contribution to journalArticle

A Practical Collision Avoidance Method for an Inter-Chip Bus with Wireless Inductive through Chip Interface

Nomura, A., Kadomoto, JI., Kuroda, T. & Amano, H., 2018 Apr 23, Proceedings - 2017 5th International Symposium on Computing and Networking, CANDAR 2017. Institute of Electrical and Electronics Engineers Inc., Vol. 2018-January. p. 126-131 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

A preemption algorithm for a multitasking environment on dynamically reconfigurable processor

Tuan, V. M. & Amano, H., 2008 Sep 22, Reconfigurable Computing: Architectures, Tools and Applications - 4th International Workshop, ARC 2008, Proceedings. p. 172-184 13 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 4943 LNCS).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A preemption algorithm for a multitasking environment on dynamically reconfigurable processors

Tuan, V. M. & Amano, H., 2008 Jan 1, In : IEICE Transactions on Information and Systems. E91-D, 12, p. 2793-2803 11 p.

Research output: Contribution to journalArticle

A preliminarily evaluation of PEACH3: A switching hub for tightly coupled accelerators

Kuhara, T., Kaneda, T., Hanawa, T., Kodama, Y., Boku, T. & Amano, H., 2015 Feb 27, Proceedings - 2014 2nd International Symposium on Computing and Networking, CANDAR 2014. Institute of Electrical and Electronics Engineers Inc., p. 377-381 5 p. 7052213. (Proceedings - 2014 2nd International Symposium on Computing and Networking, CANDAR 2014).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

A Preliminary evaluation of building block computing systems

Terashima, S., Kojima, T., Okuhara, H., Musha, K., Amano, H., Sakamoto, R., Kondo, M. & Namiki, M., 2019 Oct, Proceedings - 2019 IEEE 13th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019. Institute of Electrical and Electronics Engineers Inc., p. 312-319 8 p. 8906777. (Proceedings - 2019 IEEE 13th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A proposal of thread virtualization environment for cell broadband engine

Yamada, M., Nishikawa, Y., Yoshimi, M. & Amano, H., 2010 Dec 1, Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Systems, PDCS 2010. p. 32-39 8 p. (Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Systems).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

A prototype chip of multicontext FPGA with DRAM for virtual hardware

Kawakami, D., Shibata, Y. & Amano, H., 2001 Jan 1, Proceedings of the ASP-DAC 2001: Asia and South Pacific Design Automation Conference 2001. Institute of Electrical and Electronics Engineers Inc., p. 17-18 2 p. 913267. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; vol. 2001-January).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

A query‐based parallel logic simulation algorithm

Kudoh, T., Kimura, T., Amano, H. & Terasawa, T., 1993, In : Systems and Computers in Japan. 24, 2, p. 11-21 11 p.

Research output: Contribution to journalArticle

A rapid optimization method for visual indirect SLAM using a subset of feature points

Kazami, R. & Amano, H., 2019 Nov, Proceedings - 2019 7th International Symposium on Computing and Networking Workshops, CANDARW 2019. Institute of Electrical and Electronics Engineers Inc., p. 275-279 5 p. 8951546. (Proceedings - 2019 7th International Symposium on Computing and Networking Workshops, CANDARW 2019).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Architecture and Evaluation of a Third-Generation RHiNET Switch for High-Performance Parallel Computing

Nishi, H., Nishimura, S., Harasawa, K., Kudoh, T. & Amano, H., 2003 Oct, In : IEICE Transactions on Information and Systems. E86-D, 10, p. 1987-1995 9 p.

Research output: Contribution to journalArticle

A reconfigurable sensor-data processing system for personal robots

Nukata, K., Shibata, Y., Amano, H. & Anzai, Y., 1997, Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Springer Verlag, Vol. 1304. p. 491-500 10 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 1304).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

A reconfigurable stochastic model simulator for analysis of parallel systems

Yamamoto, O., Shibata, Y., Kurosawa, H. & Amano, H., 2000, Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Springer Verlag, Vol. 1896. p. 475-484 10 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 1896).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A reconfigurable stochastic model simulator for analysis of parallel systems

Yamamoto, O., Shibata, Y., Kurosawa, H. & Amano, H., 2000, IEEE Symposium on FPGAs for Custom Computing Machines, Proceedings. Institute of Electrical and Electronics Engineers Inc., Vol. 2000-January. p. 291-292 2 p. 903422

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

A retargetable compiler based on graph representation for dynamically reconfigurable processor arrays

Tunbunheng, V. & Amano, H., 2008 Nov, In : IEICE Transactions on Information and Systems. E91-D, 11, p. 2655-2665 11 p.

Research output: Contribution to journalArticle

3 Citations (Scopus)

A routing algorithm for multihop WDM ring

Bong, X., Kudoh, T. & Amano, H., 1999 Jan 1, In : IEICE Transactions on Information and Systems. E82-D, 2, p. 422-430 9 p.

Research output: Contribution to journalArticle

A routing strategy for inductive-coupling based wireless 3-D NoCs by maximizing topological regularity

Sasaki, D., Zhang, H., Matsutani, H., Koibuchi, M. & Amano, H., 2013 Dec 1, Algorithms and Architectures for Parallel Processing - 13th International Conference, ICA3PP 2013, Proceedings. PART 2 ed. p. 77-85 9 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 8286 LNCS, no. PART 2).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Artificial intelligence of Blokus Duo on FPGA using Cyber Work Bench

Sugimoto, N., Miyajima, T., Kuhara, T., Katuta, Y., Mitsuichi, T. & Amano, H., 2013 Dec 1, FPT 2013 - Proceedings of the 2013 International Conference on Field Programmable Technology. p. 498-501 4 p. 6718427. (FPT 2013 - Proceedings of the 2013 International Conference on Field Programmable Technology).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface

Miura, N., Koizumi, Y., Sasaki, E., Take, Y., Matsutani, H., Kuroda, T., Amano, H., Sakamoto, R., Namiki, M., Usami, K., Kondo, M. & Nakamura, H., 2016 May 24, 2013 IEEE Hot Chips 25 Symposium, HCS 2013. Institute of Electrical and Electronics Engineers Inc., 7478328. (2013 IEEE Hot Chips 25 Symposium, HCS 2013).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A scalable 3D heterogeneous multi-core processor with inductive-coupling ThruChip interface

Miura, N., Koizumi, Y., Sasaki, E., Take, Y., Matsutani, H., Kuroda, T., Amano, H., Sakamoto, R., Namiki, M., Usami, K., Kondo, M. & Nakamura, H., 2013 Aug 15, IEEE Symposium on Low-Power and High-Speed Chips - Proceedings for 2013 COOL Chips XVI. 6547916. (IEEE Symposium on Low-Power and High-Speed Chips - Proceedings for 2013 COOL Chips XVI).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

A scalable 3D heterogeneous multicore with an inductive ThruChip interface

Miura, N., Koizumi, Y., Take, Y., Matsutani, H., Kuroda, T., Amano, H., Sakamoto, R., Namiki, M., Usami, K., Kondo, M. & Nakamura, H., 2013 Nov 1, In : IEEE Micro. 33, 6, p. 6-15 10 p., 6684194.

Research output: Contribution to journalArticle

21 Citations (Scopus)

A scalable 3D processor by homogeneous chip stacking with inductive-coupling link

Kohama, Y., Sugimori, Y., Saito, S., Hasegawa, Y., Sano, T., Kasuga, K., Yoshida, Y., Niitsu, K., Miura, N., Amano, H. & Kuroda, T., 2009 Nov 18, 2009 Symposium on VLSI Circuits. p. 94-95 2 p. 5205288. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

15 Citations (Scopus)

A simple data transfer technique using local address for networks-on-chips

Koibuchi, M., Anjo, K., Yamada, Y., Jouraku, A. & Amano, H., 2006 Dec 1, In : IEEE Transactions on Parallel and Distributed Systems. 17, 12, p. 1425-1437 13 p.

Research output: Contribution to journalArticle

16 Citations (Scopus)

A speculative gather system for cool mega-array

Uno, R., Ozaki, N., Isawa, M., Tsusaka, A., Miyajima, T. & Amano, H., 2013 Dec 1, FPT 2013 - Proceedings of the 2013 International Conference on Field Programmable Technology. p. 346-349 4 p. 6718383. (FPT 2013 - Proceedings of the 2013 International Conference on Field Programmable Technology).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

A static scheduling system for a parallel machine (SM)2-II

Xiao-Ping, L. & Amano, H., 1989, PARLE 1989: Parallel Architectures and Languages Europe - Parallel Languages, Proceedings. Springer Verlag, Vol. 365 LNCS. p. 118-135 18 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 365 LNCS).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

A Stdm (static time division multiplexing) switch on a multi-fpga system

Azegami, K., Musha, K., Hironaka, K., Ben Ahmed, A., Koibuch, M., Hu, Y. & Amano, H., 2019 Oct, Proceedings - 2019 IEEE 13th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019. Institute of Electrical and Electronics Engineers Inc., p. 328-333 6 p. 8906518. (Proceedings - 2019 IEEE 13th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A study of adaptable co-processors for cyclic redundancy check on an FPGA

Akagic, A. & Amano, H., 2012 Dec 1, FPT 2012 - 2012 International Conference on Field-Programmable Technology. p. 119-124 6 p. 6412122. (FPT 2012 - 2012 International Conference on Field-Programmable Technology).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

A study on interconnection networks of the dynamically reconfigurable processor array MuCCRA

Kato, M., Sano, T., Yasuda, Y., Saito, Y. & Amano, H., 2009 Dec 1, Proceedings of the 2009 International Conference on Field-Programmable Technology, FPT'09. p. 415-418 4 p. 5377694. (Proceedings of the 2009 International Conference on Field-Programmable Technology, FPT'09).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

A study on snoop cache systems for single-chip multiprocessors

Terasawa, T., Inoue, K., Kurosawa, H. & Amano, H., 1998 Feb, In : Systems and Computers in Japan. 28, 2, p. 62-72 11 p.

Research output: Contribution to journalArticle

A survey on dynamically reconfigurable processors

Amano, H., 2006 Dec, In : IEICE Transactions on Communications. E89-B, 12, p. 3179-3187 9 p.

Research output: Contribution to journalReview article

52 Citations (Scopus)

A switch-tagged routing methodology for PC clusters with VLAN Ethernet

Koibuchi, M., Otsuka, T., Kudoh, T. & Amano, H., 2011 Jan 1, In : IEEE Transactions on Parallel and Distributed Systems. 22, 2, p. 217-230 14 p., 5445093.

Research output: Contribution to journalArticle

4 Citations (Scopus)

A switch-tagged VLAN routing methodology for PC clusters with Ethernet

Otsuka, T., Koibuchi, M., Kudoh, T. & Amano, H., 2006 Dec 1, ICPP 2006: Proceedings of the 2006 International Conference on Parallel Processing. p. 479-486 8 p. 1690652. (Proceedings of the International Conference on Parallel Processing).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Citations (Scopus)

Asymmetric Body Bias Control With Low-Power FD-SOI Technologies: Modeling and Power Optimization

Okuhara, H., Ben Ahmed, A., Kuhn, J. M. & Amano, H., 2018 Mar 23, (Accepted/In press) In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Research output: Contribution to journalArticle

8 Citations (Scopus)

A System delay monitor exploiting automatic cell-based design flow and post-silicon calibration

Okuhara, H., Kazami, R. & Amano, H., 2019 Oct, Proceedings - 2019 IEEE 13th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019. Institute of Electrical and Electronics Engineers Inc., p. 32-37 6 p. 8906740. (Proceedings - 2019 IEEE 13th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A temporal correlation based port combination methodology for Networks-on-Chip on reconfigurable systems

Wang, D., Matsutani, H., Amano, H. & Koibuchi, M., 2007 Dec 1, Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL. p. 383-388 6 p. 4380676. (Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

A thermal management system for building block computing systems

Fujita, Y., Usami, K. & Amano, H., 2014 Nov 6, Proceedings - 2014 IEEE 8th International Symposium on Embedded Multicore/Manycore SoCs, MCSoC 2014. Institute of Electrical and Electronics Engineers Inc., p. 165-171 7 p. 6949468. (Proceedings - 2014 IEEE 8th International Symposium on Embedded Multicore/Manycore SoCs, MCSoC 2014).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

A toolchain for dynamic function off-load on CPU-FPGA platforms

Miyajima, T., Thomas, D. & Amano, H., 2015 Jan 1, In : Journal of information processing. 23, 2, p. 153-162 10 p.

Research output: Contribution to journalArticle

1 Citation (Scopus)

Attempt-1: A reconfigurable multiprocessor testbed

Inoue, K., Kisuki, T., Okuno, M., Shimizu, E., Terasawa, T. & Amano, H., 1996, Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Springer Verlag, Vol. 1142. p. 200-209 10 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 1142).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Automatic pipeline construction focused on similarity of rate law functions for an FPGA-based biochemical simulator

Yamada, H., Ogawa, Y., Ooya, T., Ishimori, T., Osana, Y., Yoshimi, M., Nishikawa, Y., Funahashi, A., Hiroi, N., Amano, H., Shibata, Y. & Oguri, K., 2010 Dec 1, In : IPSJ Transactions on System LSI Design Methodology. 3, p. 244-256 13 p.

Research output: Contribution to journalArticle

2 Citations (Scopus)

A variable-pipeline on-chip router optimized to traffic pattern

Hirata, Y., Matsutani, H., Koibuchi, M. & Amano, H., 2010 Dec 1, 3rd International Workshop on Network on Chip Architectures, NoCArc 2010, in Conjunction with the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-43. p. 57-62 6 p. (3rd International Workshop on Network on Chip Architectures, NoCArc 2010, in Conjunction with the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-43).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

A vertical bubble flow network using inductive-coupling for 3-D CMPs

Matsutani, H., Take, Y., Sasaki, D., Kimura, M., Ono, Y., Nishiyama, Y., Koibuchi, M., Kuroda, T. & Amano, H., 2011 Jul 19, NOCS 2011: The 5th ACM/IEEE International Symposium on Networks-on-Chip. p. 49-56 8 p. (NOCS 2011: The 5th ACM/IEEE International Symposium on Networks-on-Chip).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

17 Citations (Scopus)

A virtual hardware system on a dynamically reconfigurable logic device

Shibata, Y., Uno, M., Amano, H., Furuta, K., Fujii, T. & Motomura, M., 2000, IEEE Symposium on FPGAs for Custom Computing Machines, Proceedings. Institute of Electrical and Electronics Engineers Inc., Vol. 2000-January. p. 295-296 2 p. 903423

Research output: Chapter in Book/Report/Conference proceedingConference contribution

11 Citations (Scopus)

AxNoC: Low-power Approximate Network-on-Chips using Critical-Path Isolation

Ahmed, A. B., Fujiki, D., Matsutani, H., Koibuchi, M. & Amano, H., 2018 Oct 26, 2018 12th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2018. Institute of Electrical and Electronics Engineers Inc., 8512158. (2018 12th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2018).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Citations (Scopus)

Balanced dimension-order routing for k-ary n-cubes

Montañana, J. M., Koibuchi, M., Matsutani, H. & Amano, H., 2009 Dec 1, ICPPW 2009 - The 38th International Conference Parallel Processing Workshops. p. 499-506 8 p. 5365405. (Proceedings of the International Conference on Parallel Processing Workshops).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Black-bus: A new data-transfer technique using local address on networks-on-chips

Anjo, K., Yamada, Y., Koibuchi, M., Jouraku, A. & Amano, H., 2004 Dec 1, Proceedings - 18th International Parallel and Distributed Processing Symposium, IPDPS 2004 (Abstracts and CD-ROM). p. 115-122 8 p. (Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2004 (Abstracts and CD-ROM); vol. 18).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)