• 2574 Citations
  • 23 h-Index
1983 …2020

Research output per year

If you made any changes in Pure these will be visible here soon.

Research Output

2009

A modular approach to heterogeneous biochemical model simulation on an FPGA

Yamada, H., Osana, Y., Ishimori, T., Ooya, T., Yoshimi, M., Nishikawa, Y., Funahashi, A., Hiroi, N., Amano, H., Shibata, Y. & Oguri, K., 2009 Dec 1, ReConFig'09 - 2009 International Conference on ReConFigurable Computing and FPGAs. p. 125-130 6 p. 5382039. (ReConFig'09 - 2009 International Conference on ReConFigurable Computing and FPGAs).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

An on/off link activation method for low-power ethernet in PC clusters

Koibuchi, M., Otsuka, T., Matsutani, H. & Amano, H., 2009 Nov 25, IPDPS 2009 - Proceedings of the 2009 IEEE International Parallel and Distributed Processing Symposium. 5161069. (IPDPS 2009 - Proceedings of the 2009 IEEE International Parallel and Distributed Processing Symposium).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Citations (Scopus)

A scalable 3D processor by homogeneous chip stacking with inductive-coupling link

Kohama, Y., Sugimori, Y., Saito, S., Hasegawa, Y., Sano, T., Kasuga, K., Yoshida, Y., Niitsu, K., Miura, N., Amano, H. & Kuroda, T., 2009 Nov 18, 2009 Symposium on VLSI Circuits. p. 94-95 2 p. 5205288. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

15 Citations (Scopus)

A study on interconnection networks of the dynamically reconfigurable processor array MuCCRA

Kato, M., Sano, T., Yasuda, Y., Saito, Y. & Amano, H., 2009 Dec 1, Proceedings of the 2009 International Conference on Field-Programmable Technology, FPT'09. p. 415-418 4 p. 5377694. (Proceedings of the 2009 International Conference on Field-Programmable Technology, FPT'09).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Balanced dimension-order routing for k-ary n-cubes

Montañana, J. M., Koibuchi, M., Matsutani, H. & Amano, H., 2009 Dec 1, ICPPW 2009 - The 38th International Conference Parallel Processing Workshops. p. 499-506 8 p. 5365405. (Proceedings of the International Conference on Parallel Processing Workshops).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Cache controller design on ultra low leakage embedded processors

Lei, Z., Xu, H., Seki, N., Yoshiki, S., Hasegawa, Y., Usami, K. & Amano, H., 2009 Apr 6, In : Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 5455 LNCS, p. 171-182 12 p.

Research output: Contribution to journalConference article

Code compression with split echo instructions

Stubdal, I., Karaduman, A. & Amano, H., 2009 Jan 1, In : IEICE Transactions on Information and Systems. E92-D, 9, p. 1650-1656 7 p.

Research output: Contribution to journalArticle

1 Citation (Scopus)

Configuring area and performance: Empirical evaluation on an FPGA-based biochemical simulator

Ooya, T., Yamada, H., Ishimori, T., Shibata, Y., Osana, Y., Oguri, K., Yoshimi, M., Nishikawa, Y., Funahashi, A., Hiroi, N. & Amano, H., 2009 Nov 25, FPL 09: 19th International Conference on Field Programmable Logic and Applications. p. 679-682 4 p. 5272335. (FPL 09: 19th International Conference on Field Programmable Logic and Applications).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Design and implementation of fine-grain power gating with ground bounce suppression

Usami, K., Shirai, T., Hashida, T., Masuda, H., Takeda, S., Nakata, M., Seki, N., Amano, H., Namiki, M., Imai, M., Kondo, M. & Nakamura, H., 2009 Mar 30, Proceedings: 22nd International Conference on VLSI Design - Held Jointly with 7th International Conference on Embedded Systems. p. 381-386 6 p. 4749703. (Proceedings: 22nd International Conference on VLSI Design - Held Jointly with 7th International Conference on Embedded Systems).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

25 Citations (Scopus)

Embedded software compression with split echo instructions

Stubdal, I., Karaduman, A. & Amano, H., 2009 Oct 27, 2009 IEEE 13th International Symposium on Consumer Electronics, ISCE 2009. p. 816-818 3 p. 5157058. (Digest of Technical Papers - IEEE International Conference on Consumer Electronics).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Evaluation of a multicore reconfigurable architecture with variable core sizes

Tuan, V. M., Katsura, N., Matsutani, H. & Amano, H., 2009 Nov 25, IPDPS 2009 - Proceedings of the 2009 IEEE International Parallel and Distributed Processing Symposium. 5161225. (IPDPS 2009 - Proceedings of the 2009 IEEE International Parallel and Distributed Processing Symposium).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Fat H-Tree: A cost-efficient tree-based on-chip network

Matsutani, H., Koibuchi, M., Yamada, Y., Hsu, D. F. & Amano, H., 2009 Jun 4, In : IEEE Transactions on Parallel and Distributed Systems. 20, 8, p. 1126-1141 16 p.

Research output: Contribution to journalArticle

18 Citations (Scopus)

Fine grain partial reconfiguration for energy saving in dynamically reconfigurable processors

Sano, T., Saito, Y., Kato, M. & Amano, H., 2009 Nov 25, FPL 09: 19th International Conference on Field Programmable Logic and Applications. p. 530-533 4 p. 5272435. (FPL 09: 19th International Conference on Field Programmable Logic and Applications).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Geyser-1: A MIPS R3000 CPU core with fine grain runtime power gating

Ikebuchi, D., Seki, N., Kojima, Y., Kamata, M., Zhao, L., Amano, H., Shirai, T., Koyamat, S., Hashida, T., Umahashi, Y., Masuda, H., Usami, K., Takeda, S., Nakamura, H., Namiki, M. & Kondo, M., 2009 Dec 1, Proceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009. p. 281-284 4 p. 5357257. (Proceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

33 Citations (Scopus)

Guest editors' introduction ICFPT 2007

Amano, H. & Nakamura, T., 2009 Jun 1, In : ACM Transactions on Reconfigurable Technology and Systems. 2, 2, 7.

Research output: Contribution to journalEditorial

Implementation and evaluation of fine-grain run-time power gating for a multiplier

Usami, K., Nakata, M., Shirai, T., Takeda, S., Seki, N., Amano, H. & Nakamura, H., 2009 Dec 1, 2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009. p. 7-10 4 p. 5166253. (2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Implementation and evaluation of self-organizing map algorithm on a graphic processor

Shitara, A., Nishikawa, Y., Yoshimi, M. & Amano, H., 2009 Dec 1, Proceedings of the 21st IASTED International Conference on Parallel and Distributed Computing and Systems, PDCS 2009. p. 253-260 8 p. (Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Systems).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Leakage power reduction for coarse-grained dynamically reconfigurable processor arrays using dual Vt cells

Hirai, K., Kato, M., Saito, Y. & Amano, H., 2009 Dec 1, Proceedings of the 2009 International Conference on Field-Programmable Technology, FPT'09. p. 104-111 8 p. 5377641. (Proceedings of the 2009 International Conference on Field-Programmable Technology, FPT'09).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Low power image processing using MuCCRA-3: A dynamically reconfigurable processor array

Kimura, M., Saito, Y., Sano, T., Kato, M., Tunbunheng, V., Yasuda, Y. & Amano, H., 2009 Dec 1, Proceedings of the 2009 International Conference on Field-Programmable Technology, FPT'09. p. 364-367 4 p. 5377614. (Proceedings of the 2009 International Conference on Field-Programmable Technology, FPT'09).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Modularizing flux limiter functions for a computational fluid dynamics accelerator on FPGAS

Inakagata, K., Morishita, H., Osana, Y., Fujita, N. & Amano, H., 2009 Nov 25, FPL 09: 19th International Conference on Field Programmable Logic and Applications. p. 654-657 4 p. 5272347. (FPL 09: 19th International Conference on Field Programmable Logic and Applications).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

MuCCRA-Cube: A 3D dynamically reconfigurable processor with inductive-coupling link

Saito, S., Kohama, Y., Sugimori, Y., Hasegawa, Y., Matsutani, H., Sano, T., Kasuga, K., Yoshida, Y., Niitsu, K., Miura, N., Kuroda, T. & Amano, H., 2009 Nov 25, FPL 09: 19th International Conference on Field Programmable Logic and Applications. p. 6-11 6 p. 5272565. (FPL 09: 19th International Conference on Field Programmable Logic and Applications).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

21 Citations (Scopus)

Performance analysis of clearspeed's CSX600 interconnects

Nishikawa, Y., Koibuchi, M., Yoshimi, M., Shitara, A., Miura, K. & Amano, H., 2009 Nov 19, Proceedings - 2009 IEEE International Symposium on Parallel and Distributed Processing with Applications, ISPA 2009. p. 203-210 8 p. 5207934. (Proceedings - 2009 IEEE International Symposium on Parallel and Distributed Processing with Applications, ISPA 2009).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Pipeline scheduling with input port constraints for an FPGA-based biochemical simulator

Ishimori, T., Yamada, H., Shibata, Y., Osana, Y., Yoshimi, M., Nishikawa, Y., Amano, H., Funahashi, A., Hiroi, N. & Oguri, K., 2009 Jun 22, In : Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 5453, p. 368-373 6 p.

Research output: Contribution to journalConference article

3 Citations (Scopus)

Prediction router: Yet another low latency on-chip router architecture

Matsutani, H., Koibuchi, M., Amano, H. & Yoshinaga, T., 2009 Apr 24, Proceedings - 15th International Symposium on High-Performance Computer Architecture, HPCA - 15 2009. p. 367-378 12 p. 4798274. (Proceedings - International Symposium on High-Performance Computer Architecture).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

60 Citations (Scopus)
2008

Adding slow-silent virtual channels for low-power on-chip networks

Matsutani, H., Koibuchi, M., Wang, D. & Amano, H., 2008 May 28, Proceedings - Second IEEE International Symposium on Networks-on-Chip, NOCS 2008. p. 23-32 10 p. 4492722. (Proceedings - Second IEEE International Symposium on Networks-on-Chip, NOCS 2008).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

33 Citations (Scopus)

A Fine-grain Dynamic Sleep Control Scheme in MIPS R3000

Seki, N., Zhao, L., Kei, J., Ikebuchi, D., Kojima, Y., Hasegawa, Y., Amano, H., Toshihiro Kashima, K., Takeda, S., Shirai, T., Nakata, M., Usami, K., Sunata, T., Kanai, J., Namiki, M., Kondo, M. & Nakamura, H., 2008 Dec 1, 26th IEEE International Conference on Computer Design 2008, ICCD. p. 612-617 6 p. 4751924. (26th IEEE International Conference on Computer Design 2008, ICCD).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

34 Citations (Scopus)

A lightweight fault-tolerant mechanism for network-on-chip

Koibuchi, M., Matsutani, H., Amano, H. & Pinkston, T. M., 2008 May 28, Proceedings - Second IEEE International Symposium on Networks-on-Chip, NOCS 2008. p. 13-22 10 p. 4492721. (Proceedings - Second IEEE International Symposium on Networks-on-Chip, NOCS 2008).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

110 Citations (Scopus)

A mapping method for multi-process execution on dynamically reconfigurable processors

Manh Tuan, V. & Amano, H., 2008 Sep, In : IEICE Transactions on Information and Systems. E91-D, 9, p. 2312-2322 11 p.

Research output: Contribution to journalArticle

4 Citations (Scopus)

A method for capturing state data on dynamically reconfigurable processors

Tuan, V. M. & Amano, H., 2008 Dec 1, Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2008. p. 208-214 7 p. (Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2008).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

A preemption algorithm for a multitasking environment on dynamically reconfigurable processor

Tuan, V. M. & Amano, H., 2008 Sep 22, Reconfigurable Computing: Architectures, Tools and Applications - 4th International Workshop, ARC 2008, Proceedings. p. 172-184 13 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 4943 LNCS).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A preemption algorithm for a multitasking environment on dynamically reconfigurable processors

Tuan, V. M. & Amano, H., 2008 Jan 1, In : IEICE Transactions on Information and Systems. E91-D, 12, p. 2793-2803 11 p.

Research output: Contribution to journalArticle

A retargetable compiler based on graph representation for dynamically reconfigurable processor arrays

Tunbunheng, V. & Amano, H., 2008 Nov, In : IEICE Transactions on Information and Systems. E91-D, 11, p. 2655-2665 11 p.

Research output: Contribution to journalArticle

3 Citations (Scopus)

Design and implementation of adaptive Viterbi decoder for using a dynamic reconfigurable processor

Kishimoto, Y., Haruyama, S. & Amano, H., 2008 Dec 1, Proceedings - 2008 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2008. p. 247-252 6 p. 4731802. (Proceedings - 2008 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2008).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

ESPRIT/sim: A high speed performance-simulator for heterogeneous embedded multiprocessors

Ohmiya, Y. & Amano, H., 2008 Dec 1, Proceedings of the 20th IASTED International Conference on Parallel and Distributed Computing and Systems, PDCS 2008. p. 252-257 6 p. (Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Systems).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Evaluation of MuCCRA-D: A dynamically reconfigurable processor with directly interconnected PEs

Kato, M., Hasegawa, Y. & Amano, H., 2008 Dec 1, Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2008. p. 215-221 7 p. (Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2008).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Exploiting memory hierarchy for a Computational Fluid Dynamics accelerator on FPGAs

Morishita, H., Osana, Y., Fujita, N. & Amano, H., 2008 Dec 1, Proceedings of the 2008 International Conference on Field-Programmable Technology, ICFPT 2008. p. 193-200 8 p. 4762383. (Proceedings of the 2008 International Conference on Field-Programmable Technology, ICFPT 2008).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Citations (Scopus)

Exploring the optimal size for multicasting configuration data of dynamically Reconfigurable processors

Nakamura, T., Sano, T., Hasegawa, Y., Tsutsumi, S., Tunbunheng, V. & Amano, H., 2008 Dec 1, Proceedings of the 2008 International Conference on Field-Programmable Technology, ICFPT 2008. p. 137-144 8 p. 4762376. (Proceedings of the 2008 International Conference on Field-Programmable Technology, ICFPT 2008).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Implementation and evaluation of the mechanisms for low latency communication on DIMMnet-2

Miyabe, Y., Kitamura, A., Hamada, Y., Miyasiro, T., Izawa, T., Tanabe, N., Nakajo, H. & Amano, H., 2008, High-Performance Computing - 6th International Symposium, ISHPC 2005 and First International Workshop on Advanced Low Power Systems, ALPS 2006, Revised Selected Papers. Springer Verlag, p. 211-218 8 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 4759 LNCS).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Instruction buffer mode for multi-context dynamically reconfigurable processors

Sano, T., Kato, M., Tsutsumi, S., Hasegawa, Y. & Amano, H., 2008 Nov 3, Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL. p. 215-220 6 p. 4629934. (Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Leakage power Reduction for coarse grained dynamically reconfigurable processor arrays with fine grained power Gating technique

Saito, Y., Shirai, T., Nakamura, T., Nishimura, T., Hasegawa, Y., Tsutsumi, S., Kashima, T., Nakata, M., Takeda, S., Usami, K. & Amano, H., 2008 Dec 1, Proceedings of the 2008 International Conference on Field-Programmable Technology, ICFPT 2008. p. 329-332 4 p. 4762410. (Proceedings of the 2008 International Conference on Field-Programmable Technology, ICFPT 2008).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

15 Citations (Scopus)

Power reduction techniques for dynamically reconfigurable processor arrays

Nishimura, T., Hirai, K., Saito, Y., Nakamura, T., Hasegawa, Y., Tsutsusmi, S., Tunbunheng, V. & Amano, H., 2008 Nov 3, Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL. p. 305-310 6 p. 4629949. (Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

17 Citations (Scopus)

Practical implementation of a network-based Stochastic biochemical simulation system on an FPGA

Yoshimi, M., Nishikawa, Y., Osana, Y., Funahashi, A., Hiroi, N., Shibata, Y., Yamada, H., Kitano, H. & Amano, H., 2008 Nov 3, Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL. p. 663-666 4 p. 4630034. (Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Run-time power gating of on-chip routers using look-ahead routing

Matsutani, H., Koibuchi, M., Amano, H. & Wang, D., 2008 Aug 21, 2008 Asia and South Pacific Design Automation Conference, ASP-DAC. p. 55-60 6 p. 4484015. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

67 Citations (Scopus)

Three-dimensional layout of on-chip tree-based networks

Matsutani, H., Koibuchi, M., Hsu, D. F. & Amano, H., 2008 Aug 15, Proceedings - 9th International Symposium on Parallel Architectures, Algorithms and Networks, I-SPAN 2008. p. 281-288 8 p. 4520228. (Proceedings of the International Symposium on Parallel Architectures, Algorithms and Networks, I-SPAN).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Citations (Scopus)
2007

A combining technique of rate law functions for a cost-effective reconfigurable biological simulator

Yamada, H., Iwanaga, N., Shibata, Y., Osana, Y., Yoshimi, M., Iwaoka, Y., Nishikawa, Y., Kojima, T., Amano, H., Funahashi, A., Hiroi, N., Hiroaki Kitano, K. & Kiyoshi Oguri, O., 2007 Dec 1, Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL. p. 808-811 4 p. 4380774. (Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

A framework for implementing a network-based stochastic biochemical simulator on an FPGA

Yoshimi, M., Nishikawa, Y., Kojima, T., Osana, Y., Funahashi, A., Hiroi, N., Shibata, Y., Yamada, H., Kitano, H. & Amano, H., 2007 Dec 1, ICFPT 2007 - International Conference on Field Programmable Technology. p. 193-200 8 p. 4439249. (ICFPT 2007 - International Conference on Field Programmable Technology).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

A high speed license plate recognition system on an FPGA

Kanamori, T., Amano, H., Arai, M., Konno, D., Nanba, T. & Ajioka, Y., 2007 Dec 1, Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL. p. 554-557 4 p. 4380715. (Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

A mapping method for multi-process execution on dynamically reconfigurable processors

Vu, M. T. & Amano, H., 2007 Dec 1, ICFPT 2007 - International Conference on Field Programmable Technology. p. 357-360 4 p. 4439285. (ICFPT 2007 - International Conference on Field Programmable Technology).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

An effective design of deadlock-free routing algorithms based on 2D turn model for irregular networks

Jouraku, A., Koibuchi, M. & Amano, H., 2007 Mar 1, In : IEEE Transactions on Parallel and Distributed Systems. 18, 3, p. 320-333 14 p.

Research output: Contribution to journalArticle

26 Citations (Scopus)

A port combination methodology for application-specific networks-on-chip on FPGAS

Wang, D., Matsutani, H., Koibuchi, M. & Amano, H., 2007 Dec, In : IEICE Transactions on Information and Systems. E90-D, 12, p. 1914-1922 9 p.

Research output: Contribution to journalArticle