• 2520 Citations
  • 23 h-Index
1983 …2020

Research output per year

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(SM)**2: SPARSE MATRIX SOLVING MACHINE.

Amano, H., Yoshida, T. & Aiso, H., 1983, Conference Proceedings - Annual Symposium on Computer Architecture. IEEE, p. 213-220 8 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

(SM)**2 -II: A NEW VERSION OF THE SPARSE MATRIX SOLVING MACHINE.

Amano, H., Boku, T., Kudoh, T. & Aiso, H., 1985, Conference Proceedings - Annual Symposium on Computer Architecture. IEEE, p. 100-107 8 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Citations (Scopus)

3D layout of spidergon, flattened butterfly and dragonfly on a chip stack with inductive coupling through chip interface

Nakahara, H., Yasudo, R., Matsutani, H., Amano, H. & Koibuchi, M., 2017 Nov 27, Proceedings - 14th International Symposium on Pervasive Systems, Algorithms and Networks, I-SPAN 2017, 11th International Conference on Frontier of Computer Science and Technology, FCST 2017 and 3rd International Symposium of Creative Computing, ISCC 2017. Institute of Electrical and Electronics Engineers Inc., Vol. 2017-November. p. 52-59 8 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

3D Shared Bus Architecture Using Inductive Coupling Interconnect

Nomura, A., Fujita, Y., Matsutani, H. & Amano, H., 2015 Nov 11, Proceedings - IEEE 9th International Symposium on Embedded Multicore/Manycore SoCs, MCSoC 2015. Institute of Electrical and Electronics Engineers Inc., p. 259-266 8 p. 7328213

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7MOPS/lemon-battery image processing demonstration with an ultra-low power reconfigurable accelerator CMA-SOTB-2

Masuyama, K., Fujita, Y., Okuhara, H. & Amano, H., 2015 Oct 7, 25th International Conference on Field Programmable Logic and Applications, FPL 2015. Institute of Electrical and Electronics Engineers Inc., 7293964

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

A 0.8-μm BiCMOS sea-of-gates implementation of the tandem banyan fast packet switch

Chiussi, F. M., Amano, H. & Tobagi, F. A., 1991, Proceedings of the Custom Integrated Circuits Conference. Publ by IEEE

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

A 2.72GOPS/11mW low power reconfigurable accelerator with a highly parallel datapath consisting of combinatorial circuits in 65nm CMOS

Ozaki, N., Yasuda, Y., Saito, Y., Ikebuchi, D., Kimura, M., Amano, H., Nakamura, H., Usami, K., Namiki, M. & Kondo, M., 2011, 2011 International Symposium on Integrated Circuits, ISIC 2011. p. 579-584 6 p. 6131929

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A 297mops/0.4mw ultra low power coarse-grained reconfigurable accelerator CMA-SOTB-2

Masuyama, K., Fujita, Y., Okuhara, H. & Amano, H., 2016 Jan 25, 2015 International Conference on ReConFigurable Computing and FPGAs, ReConFig 2015. Institute of Electrical and Electronics Engineers Inc., 7393280

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

A case for random shortcut topologies for HPC interconnects

Koibuchi, M., Matsutani, H., Amano, H., Hsu, D. F. & Casanova, H., 2012, Proceedings - International Symposium on Computer Architecture. p. 177-188 12 p. 6237016

Research output: Chapter in Book/Report/Conference proceedingConference contribution

80 Citations (Scopus)

A Case for Uni-directional Network Topologies in Large-Scale Clusters

Koibuchi, M., Totoki, T., Matsutani, H., Amano, H., Chaix, F., Fujiwara, I. & Casanova, H., 2017 Sep 22, Proceedings - 2017 IEEE International Conference on Cluster Computing, CLUSTER 2017. Institute of Electrical and Electronics Engineers Inc., Vol. 2017-September. p. 178-187 10 p. 8048929

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

A case for wireless 3D NoCs for CMPs

Matsutani, H., Bogdan, P., Marculescu, R., Take, Y., Sasaki, D., Zhang, H., Koibuchi, M., Kuroda, T. & Amano, H., 2013, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. p. 23-28 6 p. 6509553

Research output: Chapter in Book/Report/Conference proceedingConference contribution

34 Citations (Scopus)

Acceleration of ART Algorithm on an FPGA Board with Xilinx SDAccel

Okamoto, Y. & Amano, H., 2019 Nov, Proceedings - 2019 7th International Symposium on Computing and Networking Workshops, CANDARW 2019. Institute of Electrical and Electronics Engineers Inc., p. 280-284 5 p. 8951517. (Proceedings - 2019 7th International Symposium on Computing and Networking Workshops, CANDARW 2019).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Acceleration of deep recurrent neural networks with an FPGA cluster

Sun, Y., Ben Ahmed, A. & Amano, H., 2019 Jun 6, Proceedings of the 10th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, HEART 2019. Association for Computing Machinery, 18. (ACM International Conference Proceeding Series).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Acceleration of Full-PIC Simulation on a CPU-FPGA Tightly Coupled Environment

Sakai, R., Sugimoto, N., Amano, H., Miyajima, T. & Fujita, N., 2016 Dec 5, Proceedings - IEEE 10th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2016. Institute of Electrical and Electronics Engineers Inc., p. 8-14 7 p. 7774414

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Acceleration of the aggregation process in a Hall-thruster simulation using Intel FPGA SDK for OpenCL

Noda, H., Sakai, R., Miyajima, T., Fujita, N. & Amano, H., 2017 Jun 7, Proceedings of the 8th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, HEART 2017. Association for Computing Machinery, 20

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Accelerator-in-switch: A framework for tightly coupled switching hub and an accelerator with FPGA

Tsuruta, C., Kaneda, T., Nishikawa, N. & Amano, H., 2017 Oct 2, 2017 27th International Conference on Field Programmable Logic and Applications, FPL 2017. Institute of Electrical and Electronics Engineers Inc., 8056846

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

A circuit division method for high-level synthesis on multi-FPGA systems

Daiki, K., Miyajima, T. & Amano, H., 2013, Proceedings - 27th International Conference on Advanced Information Networking and Applications Workshops, WAINA 2013. p. 156-161 6 p. 6550389

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A coarse grained-reconfigurable accelerator with energy efficient MTJ-based non-volatile flip-flops

Ikezoe, T., Amano, H., Akaike, J., Usami, K., Kudo, M., Hiraga, K., Shuto, Y. & Yagami, K., 2019 Feb 13, 2018 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2018. Andrews, D., Feregrino, C., Cumplido, R. & Stroobandt, D. (eds.). Institute of Electrical and Electronics Engineers Inc., 8641712. (2018 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2018).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A combining technique of rate law functions for a cost-effective reconfigurable biological simulator

Yamada, H., Iwanaga, N., Shibata, Y., Osana, Y., Yoshimi, M., Iwaoka, Y., Nishikawa, Y., Kojima, T., Amano, H., Funahashi, A., Hiroi, N., Hiroaki Kitano, K. & Kiyoshi Oguri, O., 2007, Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL. p. 808-811 4 p. 4380774

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

A configuration data multicasting method for coarse-grained reconfigurable architectures

Kojima, T. & Amano, H., 2018 Nov 9, Proceedings - 2018 International Conference on Field-Programmable Logic and Applications, FPL 2018. Institute of Electrical and Electronics Engineers Inc., p. 239-242 4 p. 8533501. (Proceedings - 2018 International Conference on Field-Programmable Logic and Applications, FPL 2018).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

A context dependent clock control mechanism for dynamically reconfigurable processors

Amano, H., Hasegawa, Y., Abe, S., Ishikawa, K., Tsutsumi, S., Kurotaki, S., Nakamura, T. & Nishimura, T., 2006, Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL. p. 575-580 6 p. 4101031

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

A Co-processor design of an energy efficient reconfigurable accelerator CMA

Izawa, M., Ozaki, N., Koizumi, Y., Uno, R. & Amano, H., 2013, Proceedings - 2013 1st International Symposium on Computing and Networking, CANDAR 2013. p. 148-154 7 p. 6726890

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

A cost-effective context memory structure for dynamically reconfigurable processors

Suzuki, M., Hasegawa, Y., Tuan, V. M., Abe, S. & Amano, H., 2006, 20th International Parallel and Distributed Processing Symposium, IPDPS 2006. Vol. 2006. 1639433

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

ACRO: Assignment of channels in reverse order to make arbitrary routing deadlock-free

Kawano, R., Nakahara, H., Tade, S., Fujiwara, I., Matsutani, H., Koibuchi, M. & Amano, H., 2016 Aug 23, 2016 IEEE/ACIS 15th International Conference on Computer and Information Science, ICIS 2016 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 7550818

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Adaptive body bias control scheme for ultra low-power network-on-chip systems

Ben Ahmed, A., Okuhara, H., Matsutani, H., Koibuchi, M. & Amano, H., 2018 Nov 16, Proceedings - 2018 IEEE 12th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2018. Institute of Electrical and Electronics Engineers Inc., p. 146-153 8 p. 8540227

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Adaptive power gating for function units in a microprocessor

Usami, K., Hashida, T., Koyama, S., Yamamoto, T., Ikebuchi, D., Amano, H., Namiki, M., Kondo, M. & Nakamura, H., 2010, Proceedings of the 11th International Symposium on Quality Electronic Design, ISQED 2010. p. 29-37 9 p. 5450407

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Adaptive routing on the recursive diagonal torus

Funahashi, A., Hanawa, T., Kudoh, T. & Amano, H., 1997, Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Springer Verlag, Vol. 1336. p. 171-182 12 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 1336).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

A datapath classification method for FPGA-based scientific application accelerator systems

Ogawa, Y., Ooya, T., Osana, Y., Yoshimi, M., Nishikawa, Y., Funahashi, A., Hiroi, N., Amano, H., Shibata, Y. & Oguri, K., 2010, Proceedings - 2010 International Conference on Field-Programmable Technology, FPT'10. p. 441-444 4 p. 5681455

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Adding slow-silent virtual channels for low-power on-chip networks

Matsutani, H., Koibuchi, M., Wang, D. & Amano, H., 2008, Proceedings - Second IEEE International Symposium on Networks-on-Chip, NOCS 2008. p. 23-32 10 p. 4492722

Research output: Chapter in Book/Report/Conference proceedingConference contribution

33 Citations (Scopus)

A deadlock-free non-minimal fully adaptive routing using virtual cut-through switching

Nishikawa, Y., Koibuchi, M., Matsutani, H. & Amano, H., 2010, Proceedings - 2010 IEEE International Conference on Networking, Architecture and Storage, NAS 2010. p. 431-438 8 p. 5575700

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A design of one-dimensional Euler equations for fluid dynamics on FPGA

Abu Talip, M. S. & Amano, H., 2011, Proceedings of 2011 1st International Symposium on Access Spaces, ISAS 2011. p. 170-173 4 p. 5960942

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

A domain specific language and toolchain for OpenCV Runtime Binary Acceleration using GPU

Miyajima, T., Thomas, D. & Amano, H., 2012, Proceedings of the 2012 3rd International Conference on Networking and Computing, ICNC 2012. p. 175-181 7 p. 6424560

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

A dynamic link-width optimization for network-on-chip

Wang, D., Koibuchi, M., Yoneda, T., Matsutani, H. & Amano, H., 2011, Proceedings - 1st International Workshop on Cyber-Physical Systems, Networks, and Applications, CPSNA 2011, Workshop Held During RTCSA 2011. Vol. 2. p. 106-108 3 p. 602900

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

A Fine-grain Dynamic Sleep Control Scheme in MIPS R3000

Seki, N., Zhao, L., Kei, J., Ikebuchi, D., Kojima, Y., Hasegawa, Y., Amano, H., Toshihiro Kashima, K., Takeda, S., Shirai, T., Nakata, M., Usami, K., Sunata, T., Kanai, J., Namiki, M., Kondo, M. & Nakamura, H., 2008, 26th IEEE International Conference on Computer Design 2008, ICCD. p. 612-617 6 p. 4751924

Research output: Chapter in Book/Report/Conference proceedingConference contribution

34 Citations (Scopus)

A framework for implementing a network-based stochastic biochemical simulator on an FPGA

Yoshimi, M., Nishikawa, Y., Kojima, T., Osana, Y., Funahashi, A., Hiroi, N., Shibata, Y., Yamada, H., Kitano, H. & Amano, H., 2007, ICFPT 2007 - International Conference on Field Programmable Technology. p. 193-200 8 p. 4439249

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

A framework for ODE-based multimodel biochemical simulations on an FPGA

Osana, Y., Fukushima, T., Yoshimi, M., Iwaoka, Y., Funahashi, A., Hiroi, N., Shibata, Y., Iwanaga, N., Kitano, H. & Amano, H., 2005, Proceedings - 2005 International Conference on Field Programmable Logic and Applications, FPL. Vol. 2005. p. 574-577 4 p. 1515788

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

A fully pipelined FPGA architecture for stochastic simulation of chemical systems

Thomas, D. B. & Amano, H., 2013, 2013 23rd International Conference on Field Programmable Logic and Applications, FPL 2013 - Proceedings. IEEE Computer Society, 6645506

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

A general hardware design model for multicontext FPGAs

Kaneko, N. & Amano, H., 2002, Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Vol. 2438 LNCS. p. 1037-1047 11 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 2438 LNCS).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

A hardware complete detection mechanism for an energy efficient reconfigurable accelerator CMA

Tsusaka, A., Izawa, M., Uno, R., Ozaki, N. & Amano, H., 2013, 2013 23rd International Conference on Field Programmable Logic and Applications, FPL 2013 - Proceedings. IEEE Computer Society, 6645594

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

A high speed design and implementation of dynamically reconfigurable processor using 28NM SOI technology

Katagiri, T. & Amano, H., 2014 Oct 16, Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014. Institute of Electrical and Electronics Engineers Inc., 6927438

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

A high speed license plate recognition system on an FPGA

Kanamori, T., Amano, H., Arai, M., Konno, D., Nanba, T. & Ajioka, Y., 2007, Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL. p. 554-557 4 p. 4380715

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

A leakage current monitor circuit using silicon on thin BOX MOSFET for dynamic back gate bias control

Okuhara, H., Usami, K. & Amano, H., 2015 Jul 14, IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips XVIII - Proceedings. Institute of Electrical and Electronics Engineers Inc., 7158656

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A lightweight fault-tolerant mechanism for network-on-chip

Koibuchi, M., Matsutani, H., Amano, H. & Pinkston, T. M., 2008, Proceedings - Second IEEE International Symposium on Networks-on-Chip, NOCS 2008. p. 13-22 10 p. 4492721

Research output: Chapter in Book/Report/Conference proceedingConference contribution

107 Citations (Scopus)

A low latency high bandwidth network interface prototype for PC cluster

Tanabe, N., Hamada, Y., Nakajo, H., Imashiro, H., Yamamoto, J., Kudoh, T. & Amano, H., 2002, Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems. IEEE Computer Society, Vol. 2002-January. p. 87-94 8 p. 1035022

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

A low-power fault-tolerant noc using error correction and detection codes

Kojima, Y., Matsutani, H., Koibuchi, M. & Amano, H., 2010, Proceedings of the 9th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2010. p. 111-118 8 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A low power NoC router using the marching memory through type

Yasudo, R., Kagami, T., Amano, H., Nakase, Y., Watanebe, M., Oishi, T., Shimizu, T. & Nakamura, T., 2014, IEEE Symposium on Low-Power and High-Speed Chips - Proceedings for 2014 IEEE COOL Chips XVII. IEEE Computer Society, 6842960

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A low power reconfigurable accelerator using a back-gate bias control technique

Su, H., Wang, W., Kitamori, K. & Amano, H., 2013, FPT 2013 - Proceedings of the 2013 International Conference on Field Programmable Technology. p. 390-393 4 p. 6718395

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

A mapping method for multi-process execution on dynamically reconfigurable processors

Vu, M. T. & Amano, H., 2007, ICFPT 2007 - International Conference on Field Programmable Technology. p. 357-360 4 p. 4439285

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

A metamorphotic Network-on-Chip for various types of parallel applications

Tade, S., Matsutani, H., Amano, H. & Koibuchi, M., 2015 Sep 8, Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors. Institute of Electrical and Electronics Engineers Inc., Vol. 2015-September. p. 98-105 8 p. 7245715

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A method for capturing state data on dynamically reconfigurable processors

Tuan, V. M. & Amano, H., 2008, Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2008. p. 208-214 7 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)