• Source: Scopus
  • Calculated based on no. of publications stored in Pure and citations from Scopus
1983 …2021

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  • A metamorphotic Network-on-Chip for various types of parallel applications

    Tade, S., Matsutani, H., Amano, H. & Koibuchi, M., 2015 Sep 8, Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors. Institute of Electrical and Electronics Engineers Inc., Vol. 2015-September. p. 98-105 8 p. 7245715

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • A method for capturing state data on dynamically reconfigurable processors

    Tuan, V. M. & Amano, H., 2008 Dec 1, Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2008. p. 208-214 7 p. (Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2008).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    1 Citation (Scopus)
  • A Method of Partitioning Convolutional Layer to Multiple FPGAs

    Iizuka, K., Ito, K., Hironaka, K. & Amano, H., 2020 Oct 21, Proceedings - International SoC Design Conference, ISOCC 2020. Institute of Electrical and Electronics Engineers Inc., p. 25-26 2 p. 9332929. (Proceedings - International SoC Design Conference, ISOCC 2020).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • A modular approach to heterogeneous biochemical model simulation on an FPGA

    Yamada, H., Osana, Y., Ishimori, T., Ooya, T., Yoshimi, M., Nishikawa, Y., Funahashi, A., Hiroi, N., Amano, H., Shibata, Y. & Oguri, K., 2009 Dec 1, ReConFig'09 - 2009 International Conference on ReConFigurable Computing and FPGAs. p. 125-130 6 p. 5382039. (ReConFig'09 - 2009 International Conference on ReConFigurable Computing and FPGAs).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    1 Citation (Scopus)
  • A multi-Vdd dynamic variable-pipeline on-chip router for CMPs

    Matsutani, H., Hirata, Y., Koibuchi, M., Usami, K., Nakamura, H. & Amano, H., 2012, ASP-DAC 2012 - 17th Asia and South Pacific Design Automation Conference. p. 407-412 6 p. 6164982. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    14 Citations (Scopus)
  • An adaptable cluster structure of (SM)2 -II

    Saito, C., Amano, H., Kudoh, T. & Aiso, H., 1986 Jan 1, CONPAR 1986 - Conference on Algorithms and Hardware for Parallel Processing, Proceedings. Handler, W., Jeltsch, R., Lange, O., Haupt, D. & Juling, W. (eds.). Springer Verlag, p. 53-60 8 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 237 LNCS).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    2 Citations (Scopus)
  • An adaptive cryptographic accelerator for IPsec on dynamically reconfigurable processor

    Hasegawa, Y., Abe, S., Matsutani, H., Amano, H., Anjo, K. & Awashima, T., 2005, Proceedings - 2005 IEEE International Conference on Field Programmable Technology. p. 163-170 8 p. 1568541. (Proceedings - 2005 IEEE International Conference on Field Programmable Technology; vol. 2005).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    17 Citations (Scopus)
  • An adaptive Viterbi decoder on the dynamically reconfigurable processor

    Abe, S., Hasegawa, Y., Toi, T., Inuo, T. & Amano, H., 2006 Dec 1, Proceedings - 2006 IEEE International Conference on Field Programmable Technology, FPT 2006. p. 285-288 4 p. 4042451. (Proceedings - 2006 IEEE International Conference on Field Programmable Technology, FPT 2006).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    3 Citations (Scopus)
  • An ARM-based heterogeneous FPGA accelerator for hall thruster simulation

    Noda, H., Orsztynowicz, M., Iizuka, K., Miyajima, T., Fujita, N. & Amano, H., 2019 Jun 6, Proceedings of the 10th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, HEART 2019. Association for Computing Machinery, 9. (ACM International Conference Proceeding Series).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • An educational system of LSI design with free-wares for VDEC

    Morisawa, F., Kawakami, D., Tanaka, K. & Amano, H., 1999, Proceedings - 1999 IEEE International Conference on Microelectronic Systems Education: Systems Education in the 21st Century, MSE 1999. Institute of Electrical and Electronics Engineers Inc., p. 61-62 2 p. 787038. (Proceedings - 1999 IEEE International Conference on Microelectronic Systems Education: Systems Education in the 21st Century, MSE 1999).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • An emulation system of the WASMII: A data driven computer on a virtual hardware

    Shibata, Y., Ling, X. P. & Amano, H., 1996, Field-Programmable Logic: Smart Applications, New Paradigms and Compilers - 6th International Workshop on Field-Programmable Logic and Applications, FPL 1996, Proceedings. Hartenstein, R. W. & Glesner, M. (eds.). Springer Verlag, p. 55-64 10 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 1142).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    3 Citations (Scopus)
  • A network switch using optical interconnection for high performance parallel computing using PCs: High-density implementation of high-speed signals for a one-chip electronic switch with optical interconnections

    Nishimura, S., Kudoh, T., Nishi, H., Harasawa, K., Matsudaira, N., Akutsu, S., Tasyo, K. & Amano, H., 1999, Proceedings - 6th International Conference on Parallel Interconnects, PI 1999. Schenfeld, E., Kostuk, R., Lund, C. & Haney, M. (eds.). Institute of Electrical and Electronics Engineers Inc., p. 5-12 8 p. 806389. (Proceedings - 6th International Conference on Parallel Interconnects, PI 1999).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    4 Citations (Scopus)
  • A new memory module for memory intensive applications

    Tanabe, N., Hakozaki, H., Nakatake, M., Dohi, Y., Nakajo, H. & Amano, H., 2004 Dec 1, International Conference on Parallel Computing in Electrical Engineering: Workshop on System Design Automation, SDA, PARELEC 2004. p. 123-128 6 p. (International Conference on Parallel Computing in Electrical Engineering: Workshop on System Design Automation, SDA, PARELEC 2004).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    2 Citations (Scopus)
  • A new version of a parallel production system machine, MANJI-II

    Miyazaki, J., Takeda, K., Amano, H. & Aiso, H., 1989, Database Machines - 6th International Workshop, IWDM 1989, Proceedings. Springer Verlag, Vol. 368 LNCS. p. 317-330 14 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 368 LNCS).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • An extension of a temperature modeling tool hotspot 6.0 for castle-of-chips stacking

    Totoki, T., Koibuchi, M. & Amano, H., 2018 Dec 26, Proceedings - 2018 6th International Symposium on Computing and Networking Workshops, CANDARW 2018. Institute of Electrical and Electronics Engineers Inc., p. 363-369 7 p. 8590927. (Proceedings - 2018 6th International Symposium on Computing and Networking Workshops, CANDARW 2018).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • An FPGA acceleration for the kd-tree search in photon mapping

    Kuhara, T., Miyajima, T., Yoshimi, M. & Amano, H., 2013 Apr 3, Reconfigurable Computing: Architectures, Tools, and Applications - 9th International Symposium, ARC 2013, Proceedings. p. 25-36 12 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 7806 LNCS).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    6 Citations (Scopus)
  • An FPGA-based, multi-model simulation method for biochemical systems

    Osana, Y., Fukushima, T., Yoshimi, M., Iwaoka, Y., Funahashi, A., Hiroi, N., Shibata, Y., Kitano, H. & Amano, H., 2005, Proceedings - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005. 1420035. (Proceedings - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005; vol. 2005).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    4 Citations (Scopus)
  • An FPGA implementation of high throughput stochastic simulator for large-scale biochemical systems

    Yoshimi, M., Osana, Y., Iwaoka, Y., Nishikawa, Y., Kojima, T., Shibata, Y., Iwanaga, N., Funahashi, A., Hiroi, N., Kitano, H. & Amano, H., 2006 Dec 1, Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL. p. 227-232 6 p. 4100980. (Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    6 Citations (Scopus)
  • An FPGA implementation of reconfigurable real-time vision architecture

    Hiraiwa, J. & Amano, H., 2013 Aug 19, Proceedings - 27th International Conference on Advanced Information Networking and Applications Workshops, WAINA 2013. p. 150-155 6 p. 6550388. (Proceedings - 27th International Conference on Advanced Information Networking and Applications Workshops, WAINA 2013).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    15 Citations (Scopus)
  • An I/O mechanism on a dynamically reconfigurable processor - Which should be moved: Data or configuration?

    Amano, H., Abe, S., Deguchi, K. & Hasegawa, Y., 2005 Dec 1, Proceedings - 2005 International Conference on Field Programmable Logic and Applications, FPL. p. 347-352 6 p. 1515746. (Proceedings - 2005 International Conference on Field Programmable Logic and Applications, FPL; vol. 2005).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    4 Citations (Scopus)
  • An implementation methodology for Neural Network on a Low-end FPGA Board

    Wei, K., Honda, K. & Amano, H., 2020 Nov, Proceedings - 2020 8th International Symposium on Computing and Networking, CANDAR 2020. Institute of Electrical and Electronics Engineers Inc., p. 228-234 7 p. 09394383. (Proceedings - 2020 8th International Symposium on Computing and Networking, CANDAR 2020).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • An implementation of the Rijndael on Async-WASMII

    Adachi, Y., Ishikawa, K., Tsutsumi, S. & Amano, H., 2003 Jan 1, Proceedings - 2003 IEEE International Conference on Field-Programmable Technology, FPT 2003. Institute of Electrical and Electronics Engineers Inc., p. 44-51 8 p. 1275730. (Proceedings - 2003 IEEE International Conference on Field-Programmable Technology, FPT 2003).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    4 Citations (Scopus)
  • An inductive-coupling bus with collision detection scheme using magnetic field variation for 3-D network-on-chips

    Kadomoto, J., Miyata, T., Amano, H. & Kuroda, T., 2017 Feb 6, 2016 IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 - Proceedings. Institute of Electrical and Electronics Engineers Inc., p. 41-44 4 p. 7844130

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    5 Citations (Scopus)
  • An inductive-coupling link for 3-D Network-on-Chips

    Kadomoto, J., Amano, H. & Kuroda, T., 2018 May 29, Proceedings - International SoC Design Conference 2017, ISOCC 2017. Institute of Electrical and Electronics Engineers Inc., p. 150-151 2 p. (Proceedings - International SoC Design Conference 2017, ISOCC 2017).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • An on/off link activation method for low-power ethernet in PC clusters

    Koibuchi, M., Otsuka, T., Matsutani, H. & Amano, H., 2009, IPDPS 2009 - Proceedings of the 2009 IEEE International Parallel and Distributed Processing Symposium. 5161069. (IPDPS 2009 - Proceedings of the 2009 IEEE International Parallel and Distributed Processing Symposium).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    12 Citations (Scopus)
  • An optimal power supply and body bias voltage for a ultra low power micro-controller with silicon on thin box MOSFET

    Okuhara, H., Kitamori, K., Fujita, Y., Usami, K. & Amano, H., 2015 Sep 21, Proceedings of the International Symposium on Low Power Electronics and Design. Institute of Electrical and Electronics Engineers Inc., Vol. 2015-September. p. 207-212 6 p. 7273515

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    13 Citations (Scopus)
  • An trace-driven performance prediction method for exploring noc design optimization

    Niwa, N., Totoki, T., Matsutani, H., Koibuchi, M. & Amano, H., 2018 Dec 26, Proceedings - 2018 6th International Symposium on Computing and Networking Workshops, CANDARW 2018. Institute of Electrical and Electronics Engineers Inc., p. 182-185 4 p. 8590896. (Proceedings - 2018 6th International Symposium on Computing and Networking Workshops, CANDARW 2018).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • A packet forwarding layer for DIMMnet and its hardware implementation

    Hamada, Y., Nishi, H., Kitamura, A., Tanabe, N., Amano, H. & Nakajo, H., 2005 Dec 1, Proceedings of the 2005 International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA'05. p. 461-467 7 p. (Proceedings of the 2005 International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA'05; vol. 2).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • A performance evaluation of CUBE: One-dimensional 512 FPGA cluster

    Yoshimi, M., Nishikawa, Y., Miki, M., Hiroyasu, T., Amano, H. & Mencer, O., 2010 Apr 29, Reconfigurable Computing: Architectures, Tools and Applications - 6th International Symposium, ARC 2010, Proceedings. p. 372-381 10 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 5992 LNCS).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    6 Citations (Scopus)
  • A perpetuum mobile 32bit CPU on 65nm SOTB CMOS technology with reverse-body-bias assisted sleep mode

    Kamohara, S., Sugii, N., Ishibashi, K., Usami, K., Amano, H., Kobayashi, K. & Pham, C. K., 2016 May 25, 2014 IEEE Hot Chips 26 Symposium, HCS 2014. Institute of Electrical and Electronics Engineers Inc., 7478838

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14μA sleep current using Reverse Body Bias Assisted 65nm SOTB CMOS technology

    Ishibashi, K., Sugii, N., Usami, K., Amano, H., Kobayashi, K., Pham, C. K., Makiyama, H., Yamamoto, Y., Shinohara, H., Iwamatsu, T., Yamaguchi, Y., Oda, H., Hasegawa, T., Okanishi, S., Yanagita, H., Kamohara, S., Kadoshima, M., Maekawa, K., Yamashita, T., Le, D. H. & 5 others, Yomogita, T., Kudo, M., Kitamori, K., Kondo, S. & Manzawa, Y., 2014, IEEE Symposium on Low-Power and High-Speed Chips - Proceedings for 2014 IEEE COOL Chips XVII. IEEE Computer Society, 6842954. (IEEE Symposium on Low-Power and High-Speed Chips - Proceedings for 2014 IEEE COOL Chips XVII).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    21 Citations (Scopus)
  • A Practical Collision Avoidance Method for an Inter-Chip Bus with Wireless Inductive through Chip Interface

    Nomura, A., Kadomoto, JI., Kuroda, T. & Amano, H., 2018 Apr 23, Proceedings - 2017 5th International Symposium on Computing and Networking, CANDAR 2017. Institute of Electrical and Electronics Engineers Inc., Vol. 2018-January. p. 126-131 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    1 Citation (Scopus)
  • A preemption algorithm for a multitasking environment on dynamically reconfigurable processor

    Tuan, V. M. & Amano, H., 2008 Sep 22, Reconfigurable Computing: Architectures, Tools and Applications - 4th International Workshop, ARC 2008, Proceedings. p. 172-184 13 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 4943 LNCS).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • A preliminarily evaluation of PEACH3: A switching hub for tightly coupled accelerators

    Kuhara, T., Kaneda, T., Hanawa, T., Kodama, Y., Boku, T. & Amano, H., 2015 Feb 27, Proceedings - 2014 2nd International Symposium on Computing and Networking, CANDAR 2014. Institute of Electrical and Electronics Engineers Inc., p. 377-381 5 p. 7052213. (Proceedings - 2014 2nd International Symposium on Computing and Networking, CANDAR 2014).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    6 Citations (Scopus)
  • A Preliminary evaluation of building block computing systems

    Terashima, S., Kojima, T., Okuhara, H., Musha, K., Amano, H., Sakamoto, R., Kondo, M. & Namiki, M., 2019 Oct, Proceedings - 2019 IEEE 13th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019. Institute of Electrical and Electronics Engineers Inc., p. 312-319 8 p. 8906777. (Proceedings - 2019 IEEE 13th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • A programming environment for multi-FPGA systems based on CyberWorkBench: An integrated design tool

    Suzuki, H., Takahashi, W., Wakabayashi, K. & Amano, H., 2021 Jun 21, Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, HEART 2021. Association for Computing Machinery, 5. (ACM International Conference Proceeding Series).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • A proposal of thread virtualization environment for cell broadband engine

    Yamada, M., Nishikawa, Y., Yoshimi, M. & Amano, H., 2010, Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Systems, PDCS 2010. p. 32-39 8 p. (Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Systems).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    2 Citations (Scopus)
  • A prototype chip of multicontext FPGA with DRAM for virtual hardware

    Kawakami, D., Shibata, Y. & Amano, H., 2001 Jan 1, Proceedings of the ASP-DAC 2001: Asia and South Pacific Design Automation Conference 2001. Institute of Electrical and Electronics Engineers Inc., p. 17-18 2 p. 913267. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; vol. 2001-January).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    7 Citations (Scopus)
  • A rapid optimization method for visual indirect SLAM using a subset of feature points

    Kazami, R. & Amano, H., 2019 Nov, Proceedings - 2019 7th International Symposium on Computing and Networking Workshops, CANDARW 2019. Institute of Electrical and Electronics Engineers Inc., p. 275-279 5 p. 8951546. (Proceedings - 2019 7th International Symposium on Computing and Networking Workshops, CANDARW 2019).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • A reconfigurable sensor-data processing system for personal robots

    Nukata, K., Shibata, Y., Amano, H. & Anzai, Y., 1997, Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Springer Verlag, Vol. 1304. p. 491-500 10 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 1304).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    2 Citations (Scopus)
  • A reconfigurable stochastic model simulator for analysis of parallel systems

    Yamamoto, O., Shibata, Y., Kurosawa, H. & Amano, H., 2000, IEEE Symposium on FPGAs for Custom Computing Machines, Proceedings. Institute of Electrical and Electronics Engineers Inc., Vol. 2000-January. p. 291-292 2 p. 903422

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    2 Citations (Scopus)
  • A reconfigurable stochastic model simulator for analysis of parallel systems

    Yamamoto, O., Shibata, Y., Kurosawa, H. & Amano, H., 2000, Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing - 10th International Conference, FPL 2000, Proceedings. Hartenstein, R. W. & Grunbacher, H. (eds.). Springer Verlag, p. 475-484 10 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 1896).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • A routing strategy for inductive-coupling based wireless 3-D NoCs by maximizing topological regularity

    Sasaki, D., Zhang, H., Matsutani, H., Koibuchi, M. & Amano, H., 2013 Dec 1, Algorithms and Architectures for Parallel Processing - 13th International Conference, ICA3PP 2013, Proceedings. PART 2 ed. p. 77-85 9 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 8286 LNCS, no. PART 2).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • Artificial intelligence of Blokus Duo on FPGA using Cyber Work Bench

    Sugimoto, N., Miyajima, T., Kuhara, T., Katuta, Y., Mitsuichi, T. & Amano, H., 2013 Dec 1, FPT 2013 - Proceedings of the 2013 International Conference on Field Programmable Technology. p. 498-501 4 p. 6718427. (FPT 2013 - Proceedings of the 2013 International Conference on Field Programmable Technology).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    3 Citations (Scopus)
  • A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface

    Miura, N., Koizumi, Y., Sasaki, E., Take, Y., Matsutani, H., Kuroda, T., Amano, H., Sakamoto, R., Namiki, M., Usami, K., Kondo, M. & Nakamura, H., 2016 May 24, 2013 IEEE Hot Chips 25 Symposium, HCS 2013. Institute of Electrical and Electronics Engineers Inc., 7478328. (2013 IEEE Hot Chips 25 Symposium, HCS 2013).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • A scalable 3D heterogeneous multi-core processor with inductive-coupling ThruChip interface

    Miura, N., Koizumi, Y., Sasaki, E., Take, Y., Matsutani, H., Kuroda, T., Amano, H., Sakamoto, R., Namiki, M., Usami, K., Kondo, M. & Nakamura, H., 2013 Aug 15, IEEE Symposium on Low-Power and High-Speed Chips - Proceedings for 2013 COOL Chips XVI. 6547916. (IEEE Symposium on Low-Power and High-Speed Chips - Proceedings for 2013 COOL Chips XVI).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    1 Citation (Scopus)
  • A scalable 3D processor by homogeneous chip stacking with inductive-coupling link

    Kohama, Y., Sugimori, Y., Saito, S., Hasegawa, Y., Sano, T., Kasuga, K., Yoshida, Y., Niitsu, K., Miura, N., Amano, H. & Kuroda, T., 2009 Nov 18, 2009 Symposium on VLSI Circuits. p. 94-95 2 p. 5205288. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    15 Citations (Scopus)
  • A speculative gather system for cool mega-array

    Uno, R., Ozaki, N., Isawa, M., Tsusaka, A., Miyajima, T. & Amano, H., 2013 Dec 1, FPT 2013 - Proceedings of the 2013 International Conference on Field Programmable Technology. p. 346-349 4 p. 6718383. (FPT 2013 - Proceedings of the 2013 International Conference on Field Programmable Technology).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    1 Citation (Scopus)
  • A static scheduling system for a parallel machine (SM)2-II

    Xiao-Ping, L. & Amano, H., 1989, PARLE 1989: Parallel Architectures and Languages Europe - Parallel Languages, Proceedings. Springer Verlag, Vol. 365 LNCS. p. 118-135 18 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 365 LNCS).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    4 Citations (Scopus)
  • A Stdm (static time division multiplexing) switch on a multi-fpga system

    Azegami, K., Musha, K., Hironaka, K., Ben Ahmed, A., Koibuch, M., Hu, Y. & Amano, H., 2019 Oct, Proceedings - 2019 IEEE 13th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019. Institute of Electrical and Electronics Engineers Inc., p. 328-333 6 p. 8906518. (Proceedings - 2019 IEEE 13th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    6 Citations (Scopus)