• 2531 Citations
  • 23 h-Index
1983 …2020

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Attempt-1: A reconfigurable multiprocessor testbed

Inoue, K., Kisuki, T., Okuno, M., Shimizu, E., Terasawa, T. & Amano, H., 1996, Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Springer Verlag, Vol. 1142. p. 200-209 10 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 1142).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

A variable-pipeline on-chip router optimized to traffic pattern

Hirata, Y., Matsutani, H., Koibuchi, M. & Amano, H., 2010 Dec 1, 3rd International Workshop on Network on Chip Architectures, NoCArc 2010, in Conjunction with the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-43. p. 57-62 6 p. (3rd International Workshop on Network on Chip Architectures, NoCArc 2010, in Conjunction with the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-43).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

A vertical bubble flow network using inductive-coupling for 3-D CMPs

Matsutani, H., Take, Y., Sasaki, D., Kimura, M., Ono, Y., Nishiyama, Y., Koibuchi, M., Kuroda, T. & Amano, H., 2011 Jul 19, NOCS 2011: The 5th ACM/IEEE International Symposium on Networks-on-Chip. p. 49-56 8 p. (NOCS 2011: The 5th ACM/IEEE International Symposium on Networks-on-Chip).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

17 Citations (Scopus)

A virtual hardware system on a dynamically reconfigurable logic device

Shibata, Y., Uno, M., Amano, H., Furuta, K., Fujii, T. & Motomura, M., 2000, IEEE Symposium on FPGAs for Custom Computing Machines, Proceedings. Institute of Electrical and Electronics Engineers Inc., Vol. 2000-January. p. 295-296 2 p. 903423

Research output: Chapter in Book/Report/Conference proceedingConference contribution

11 Citations (Scopus)

AxNoC: Low-power Approximate Network-on-Chips using Critical-Path Isolation

Ahmed, A. B., Fujiki, D., Matsutani, H., Koibuchi, M. & Amano, H., 2018 Oct 26, 2018 12th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2018. Institute of Electrical and Electronics Engineers Inc., 8512158. (2018 12th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2018).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Citations (Scopus)

Balanced dimension-order routing for k-ary n-cubes

Montañana, J. M., Koibuchi, M., Matsutani, H. & Amano, H., 2009 Dec 1, ICPPW 2009 - The 38th International Conference Parallel Processing Workshops. p. 499-506 8 p. 5365405. (Proceedings of the International Conference on Parallel Processing Workshops).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Black-bus: A new data-transfer technique using local address on networks-on-chips

Anjo, K., Yamada, Y., Koibuchi, M., Jouraku, A. & Amano, H., 2004 Dec 1, Proceedings - 18th International Parallel and Distributed Processing Symposium, IPDPS 2004 (Abstracts and CD-ROM). p. 115-122 8 p. (Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2004 (Abstracts and CD-ROM); vol. 18).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Body bias control for a coarse grained reconfigurable accelerator implemented with Silicon on Thin BOX technology

Su, H., Fujita, Y. & Amano, H., 2014 Oct 16, Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014. Institute of Electrical and Electronics Engineers Inc., 6927486. (Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

13 Citations (Scopus)

Body bias control for renewable energy source with a high inner resistance

Azegami, K., Okuhara, H. & Amano, H., 2017 Jun 12, Proceedings for 2017 IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips 2017. Institute of Electrical and Electronics Engineers Inc., 7946386

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Body bias grain size exploration for a coarse grained reconfigurable accelerator

Matsushita, Y., Okuhara, H., Masuyama, K., Fujita, Y., Kawano, R. & Amano, H., 2016 Sep 26, FPL 2016 - 26th International Conference on Field-Programmable Logic and Applications. Institute of Electrical and Electronics Engineers Inc., 7577346

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Body bias optimization for variable pipelined CGRA

Kojima, T., Ando, N., Okuhara, H., Doan, N. A. V. & Amano, H., 2017 Oct 2, 2017 27th International Conference on Field Programmable Logic and Applications, FPL 2017. Institute of Electrical and Electronics Engineers Inc., 8056851

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Break even time analysis using empirical overhead parameters for embedded systems on SOTB technology

Cortes, C., Amano, H. & Yamasaki, N., 2018 Mar 9, 2017 32nd Conference on Design of Circuits and Integrated Systems, DCIS 2017 - Proceedings. Institute of Electrical and Electronics Engineers Inc., Vol. 2017-November. p. 1-6 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Building block multi-chip systems using inductive coupling through chip interface

Amano, H., Kuroda, T., Nakamura, H., Usami, K., Kondo, M., Matsutani, H. & Namiki, M., 2018 May 29, Proceedings - International SoC Design Conference 2017, ISOCC 2017. Institute of Electrical and Electronics Engineers Inc., p. 152-154 3 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Building block operating system for 3D stacked computer systems with inductive coupling interconnect

Hamada, S., Koshiba, A., Namiki, M. & Amano, H., 2018 May 29, Proceedings - International SoC Design Conference 2017, ISOCC 2017. Institute of Electrical and Electronics Engineers Inc., p. 157-158 2 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

C4: An FPGA-based compression algorithm for expether

Shimura, H., Noda, H. & Amano, H., 2018 Dec 26, Proceedings - 2018 6th International Symposium on Computing and Networking Workshops, CANDARW 2018. Institute of Electrical and Electronics Engineers Inc., p. 356-362 7 p. 8590926. (Proceedings - 2018 6th International Symposium on Computing and Networking Workshops, CANDARW 2018).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Cache coherence protocol for home proxy cache on RHiNET and its preliminary performance estimation

Nakajo, J., Ishii, M., Yamamoto, J., Kudo, T., Yokoyama, T., Tsuchiya, J. & Amano, H., 2000, Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems. IEEE Computer Society, Vol. 2001-January. p. 53-60 8 p. 955197

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Castle of chips: A new chip stacking structure with wireless inductive coupling for large scale 3-D multicore systems

Amano, H., 2012 Dec 14, Proceedings of the 2012 15th International Conference on Network-Based Information Systems, NBIS 2012. p. 820-825 6 p. 6354931. (Proceedings of the 2012 15th International Conference on Network-Based Information Systems, NBIS 2012).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

CMA-2: The second prototype of a low power reconfigurable accelerator

Izawa, M., Ozaki, N., Yasuda, Y., Kimura, M. & Amano, H., 2012 Apr 26, ASP-DAC 2012 - 17th Asia and South Pacific Design Automation Conference. p. 471-472 2 p. 6164996. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

CMA-Cube: A scalable reconfigurable accelerator with 3-D wireless inductive coupling interconnect

Koizumi, Y., Sasaki, E., Amano, H., Matsutani, H., Take, Y., Kuroda, T., Sakamoto, R., Namiki, M., Usami, K., Kondo, M. & Nakamura, H., 2012 Dec 12, Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012. p. 543-546 4 p. 6339375. (Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Configuring area and performance: Empirical evaluation on an FPGA-based biochemical simulator

Ooya, T., Yamada, H., Ishimori, T., Shibata, Y., Osana, Y., Oguri, K., Yoshimi, M., Nishikawa, Y., Funahashi, A., Hiroi, N. & Amano, H., 2009 Nov 25, FPL 09: 19th International Conference on Field Programmable Logic and Applications. p. 679-682 4 p. 5272335. (FPL 09: 19th International Conference on Field Programmable Logic and Applications).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Cool mega-array: A highly energy efficient reconfigurable accelerator

Ozaki, N., Yoshihiro, Y., Saito, Y., Ikebuchi, D., Kimura, M., Amano, H., Nakamura, H., Usami, K., Namiki, M. & Kondo, M., 2011 Dec 1, 2011 International Conference on Field-Programmable Technology, FPT 2011. 6132668. (2011 International Conference on Field-Programmable Technology, FPT 2011).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

13 Citations (Scopus)

Cost effective implementation of flux limiter functions using partial reconfiguration

Abu Talip, M. S., Akamine, T., Osana, Y., Fujita, N. & Amano, H., 2012 Apr 11, Reconfigurable Computing: Architectures, Tools and Applications - 8th International Symposium, ARC 2012, Proceedings. p. 215-226 12 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 7199 LNCS).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Dataflow partitioning and scheduling algorithms for WASMII, a virtual hardware

Takayama, A., Shibata, Y., Iwai, K. & Amano, H., 2000, Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Springer Verlag, Vol. 1896. p. 685-694 10 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 1896).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Citations (Scopus)

Deadlock-free layered routing for infiniband networks

Kawano, R., Matsutani, H. & Amano, H., 2019 Nov, Proceedings - 2019 7th International Symposium on Computing and Networking Workshops, CANDARW 2019. Institute of Electrical and Electronics Engineers Inc., p. 84-90 7 p. 8951557. (Proceedings - 2019 7th International Symposium on Computing and Networking Workshops, CANDARW 2019).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Deep learning on high performance FPGA switching boards: Flow-in-cloud

Musha, K., Kudoh, T. & Amano, H., 2018 Jan 1, Applied Reconfigurable Computing: Architectures, Tools, and Applications - 14th International Symposium, ARC 2018, Proceedings. Springer Verlag, p. 43-54 12 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 10824 LNCS).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Demonstration of flow-in-cloud: A multi-FPGA system

Hironaka, K., Iizuka, K., Ben Ahmed, A., Imdad Ullah, M. M., Yamauchi, Y., Sun, Y., Yamakura, M., Hiruma, A. & Amano, H., 2019 Sep, Proceedings - 29th International Conference on Field-Programmable Logic and Applications, FPL 2019. Sourdis, I., Bouganis, C-S., Alvarez, C., Toledo Diaz, L. A., Valero, P. & Martorell, X. (eds.). Institute of Electrical and Electronics Engineers Inc., p. 417-418 2 p. 8892139. (Proceedings - 29th International Conference on Field-Programmable Logic and Applications, FPL 2019).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Demonstration of low power stream processing using a variable pipelined CGRA

Kojima, T., Ando, N., Matsushita, Y. & Amano, H., 2019 Sep, Proceedings - 29th International Conference on Field-Programmable Logic and Applications, FPL 2019. Sourdis, I., Bouganis, C-S., Alvarez, C., Toledo Diaz, L. A., Valero, P. & Martorell, X. (eds.). Institute of Electrical and Electronics Engineers Inc., p. 411-412 2 p. 8892240. (Proceedings - 29th International Conference on Field-Programmable Logic and Applications, FPL 2019).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Descending layers routing: A deadlock-free deterministic routing using virtual channels in system area networks with irregular topologies

Koibuchi, M., Jouraku, A., Watanabe, K. & Amano, H., 2003 Jan 1, Proceedings - 2003 International Conference on Parallel Processing, ICPP 2003. Sadayappan, P. & Yang, C-S. (eds.). Institute of Electrical and Electronics Engineers Inc., p. 527-536 10 p. 1240620. (Proceedings of the International Conference on Parallel Processing; vol. 2003-January).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

21 Citations (Scopus)

Design and control methodology for fine grain power gating based on energy characterization and code profiling of microprocessors

Usami, K., Kudo, M., Matsunaga, K., Kosaka, T., Tsurui, Y., Wang, W., Amano, H., Kobayashi, H., Sakamoto, R., Namiki, M., Kondo, M. & Nakamura, H., 2014 Mar 27, 2014 19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014 - Proceedings. p. 843-848 6 p. 6742995. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Citations (Scopus)

Design and evaluation of fine-grained power-gating for embedded microprocessors

Kondo, M., Kobyashi, H., Sakamoto, R., Wada, M., Tsukamoto, J., Namiki, M., Wang, W., Amano, H., Matsunaga, K., Kudo, M., Usami, K., Komoda, T. & Nakamura, H., 2014 Jan 1, Proceedings - Design, Automation and Test in Europe, DATE 2014. Institute of Electrical and Electronics Engineers Inc., 6800359. (Proceedings -Design, Automation and Test in Europe, DATE).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

14 Citations (Scopus)

Design and implementation of adaptive Viterbi decoder for using a dynamic reconfigurable processor

Kishimoto, Y., Haruyama, S. & Amano, H., 2008 Dec 1, Proceedings - 2008 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2008. p. 247-252 6 p. 4731802. (Proceedings - 2008 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2008).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Design and implementation of fine-grain power gating with ground bounce suppression

Usami, K., Shirai, T., Hashida, T., Masuda, H., Takeda, S., Nakata, M., Seki, N., Amano, H., Namiki, M., Imai, M., Kondo, M. & Nakamura, H., 2009 Mar 30, Proceedings: 22nd International Conference on VLSI Design - Held Jointly with 7th International Conference on Embedded Systems. p. 381-386 6 p. 4749703. (Proceedings: 22nd International Conference on VLSI Design - Held Jointly with 7th International Conference on Embedded Systems).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

25 Citations (Scopus)

Design automation methodology of a critical path monitor for adaptive voltage controls

Kazami, R., Okuhara, H. & Amano, H., 2018 Jun 5, 21st IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL Chips 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc., p. 1-3 3 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Design methodology and trade-offs analysis for parameterized dynamically reconfigurable processor arrays

Hasegawa, Y., Tsutsumi, S., Tanbunheng, V., Nakamura, T., Nishimura, T. & Amano, H., 2007 Dec 1, Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL. p. 796-799 4 p. 4380771. (Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Design of a low power NoC router using marching memory through type

Yasudo, R., Kagami, T., Amano, H., Nakase, Y., Watanabe, M., Oishi, T., Shimizu, T. & Nakamura, T., 2015 Jan 13, Proceedings - 2014 8th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2014. Bertozzi, D., Benini, L., Yalamanchili, S. & Henkel, J. (eds.). Institute of Electrical and Electronics Engineers Inc., p. 111-118 8 p. 7008769. (Proceedings - 2014 8th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2014).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Destination bundle: A routing table reduction technique for distributed routing on dependablenetworks-on-chips

Matsutani, H., Koibuchi, M. & Amano, H., 2005 Dec 1, Proceedings of the 2005 International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA'05. p. 1343-1349 7 p. (Proceedings of the 2005 International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA'05; vol. 3).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Digital embedded memory scheme using voltage scaling and body bias separation for low-power system

Yoshida, Y., Usami, K. & Amano, H., 2018 May 29, Proceedings - International SoC Design Conference 2017, ISOCC 2017. Institute of Electrical and Electronics Engineers Inc., p. 148-149 2 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

DIMMnet-2: A reconfigurable board connected into a memory slot

Miyashiro, T., Kitamura, A., Yoshimi, M., Amano, H., Nakajyo, H. & Tanabe, N., 2006 Dec 1, Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL. p. 825-828 4 p. 4101085. (Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

D-tdma data buses with CSMA/CD arbitration bus on wireless 3D IC

Matsumura, G., Koibuchi, M., Amano, H. & Matsutani, H., 2016, Proceedings of the 13th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2016. Acta Press, p. 242-249 8 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Dynamically reconfigurable flux limiter functions in MUSCL scheme

Talip, M. S. A., Akamine, T., Osana, Y., Fujita, N. & Amano, H., 2012 Nov 23, ReCoSoC 2012 - 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip, Proceedings. 6322878. (ReCoSoC 2012 - 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip, Proceedings).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Dynamic power control with a heterogeneous multi-core system using a 3-D wireless inductive coupling interconnect

Koizumi, Y., Amano, H., Matsutani, H., Miura, N., Kuroda, T., Sakamoto, R., Namiki, M., Usami, K., Kondo, M. & Nakamura, H., 2012 Dec 1, FPT 2012 - 2012 International Conference on Field-Programmable Technology. p. 293-296 4 p. 6412150. (FPT 2012 - 2012 International Conference on Field-Programmable Technology).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Dynamic power on/off method for 3D NoCs with wireless inductive-coupling links

Zhang, H., Matsutani, H., Koibuchi, M. & Amano, H., 2013 Aug 15, IEEE Symposium on Low-Power and High-Speed Chips - Proceedings for 2013 COOL Chips XVI. 6547924. (IEEE Symposium on Low-Power and High-Speed Chips - Proceedings for 2013 COOL Chips XVI).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Dynamic VDD switching technique and mapping optimization in dynamically reconfigurable processor for efficient energy reduction

Yamamoto, T., Hironaka, K., Hayakawa, Y., Kimura, M., Amano, H. & Usami, K., 2011 Apr 4, Reconfigurable Computing: Architectures, Tools and Applications - 7th International Symposium, ARC 2011, Proceedings. p. 230-241 12 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 6578 LNCS).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Citations (Scopus)

Efficient scheduling of rate law functions for ODE-based multimodel biochemical simulation on an FPGA

Iwanagra, N., Shibata, Y., Yoshimi, M., Osana, Y., Iwaoka, Y., Fukushima, T., Amano, H., Funahashi, A., Hiroi, N., Kitano, H. & Oguri, K., 2005 Dec 1, Proceedings - 2005 International Conference on Field Programmable Logic and Applications, FPL. p. 666-669 4 p. 1515809. (Proceedings - 2005 International Conference on Field Programmable Logic and Applications, FPL; vol. 2005).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Citations (Scopus)

Embedded software compression with split echo instructions

Stubdal, I., Karaduman, A. & Amano, H., 2009 Oct 27, 2009 IEEE 13th International Symposium on Consumer Electronics, ISCE 2009. p. 816-818 3 p. 5157058. (Digest of Technical Papers - IEEE International Conference on Consumer Electronics).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Energy Efficient Write Verify and Retry Scheme for MTJ Based Flip-Flop and Application

Usami, K., Akaike, J., Akiba, S., Kudo, M., Amano, H., Ikezoe, T., Hiraga, K., Shuto, Y. & Yagami, K., 2018 Nov 15, Proceedings - 7th IEEE Non-Volatile Memory Systems and Applications Symposium, NVMSA 2018. Institute of Electrical and Electronics Engineers Inc., p. 91-98 8 p. 8537701

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Enforcing dimension-order routing in on-chip torus networks without virtual channels

Matsutani, H., Koibuchi, M. & Amano, H., 2006, Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Springer Verlag, Vol. 4330. p. 207-218 12 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 4330).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

ESPRIT/sim: A high speed performance-simulator for heterogeneous embedded multiprocessors

Ohmiya, Y. & Amano, H., 2008 Dec 1, Proceedings of the 20th IASTED International Conference on Parallel and Distributed Computing and Systems, PDCS 2008. p. 252-257 6 p. (Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Systems).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Evaluation of a multicore reconfigurable architecture with variable core sizes

Tuan, V. M., Katsura, N., Matsutani, H. & Amano, H., 2009 Nov 25, IPDPS 2009 - Proceedings of the 2009 IEEE International Parallel and Distributed Processing Symposium. 5161225. (IPDPS 2009 - Proceedings of the 2009 IEEE International Parallel and Distributed Processing Symposium).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Evaluation of MuCCRA-D: A dynamically reconfigurable processor with directly interconnected PEs

Kato, M., Hasegawa, Y. & Amano, H., 2008 Dec 1, Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2008. p. 215-221 7 p. (Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2008).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)