• Source: Scopus
  • Calculated based on no. of publications stored in Pure and citations from Scopus
1983 …2021

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  • Dynamic VDD switching technique and mapping optimization in dynamically reconfigurable processor for efficient energy reduction

    Yamamoto, T., Hironaka, K., Hayakawa, Y., Kimura, M., Amano, H. & Usami, K., 2011, Reconfigurable Computing: Architectures, Tools and Applications - 7th International Symposium, ARC 2011, Proceedings. p. 230-241 12 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 6578 LNCS).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    9 Citations (Scopus)
  • Efficient scheduling of rate law functions for ODE-based multimodel biochemical simulation on an FPGA

    Iwanagra, N., Shibata, Y., Yoshimi, M., Osana, Y., Iwaoka, Y., Fukushima, T., Amano, H., Funahashi, A., Hiroi, N., Kitano, H. & Oguri, K., 2005 Dec 1, Proceedings - 2005 International Conference on Field Programmable Logic and Applications, FPL. p. 666-669 4 p. 1515809. (Proceedings - 2005 International Conference on Field Programmable Logic and Applications, FPL; vol. 2005).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    10 Citations (Scopus)
  • Embedded software compression with split echo instructions

    Stubdal, I., Karaduman, A. & Amano, H., 2009 Oct 27, 2009 IEEE 13th International Symposium on Consumer Electronics, ISCE 2009. p. 816-818 3 p. 5157058. (Digest of Technical Papers - IEEE International Conference on Consumer Electronics).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    1 Citation (Scopus)
  • Energy Efficient Write Verify and Retry Scheme for MTJ Based Flip-Flop and Application

    Usami, K., Akaike, J., Akiba, S., Kudo, M., Amano, H., Ikezoe, T., Hiraga, K., Shuto, Y. & Yagami, K., 2018 Nov 15, Proceedings - 7th IEEE Non-Volatile Memory Systems and Applications Symposium, NVMSA 2018. Institute of Electrical and Electronics Engineers Inc., p. 91-98 8 p. 8537701. (Proceedings - 7th IEEE Non-Volatile Memory Systems and Applications Symposium, NVMSA 2018).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    4 Citations (Scopus)
  • Enforcing dimension-order routing in on-chip torus networks without virtual channels

    Matsutani, H., Koibuchi, M. & Amano, H., 2006, Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Springer Verlag, Vol. 4330. p. 207-218 12 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 4330).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    1 Citation (Scopus)
  • ESPRIT/sim: A high speed performance-simulator for heterogeneous embedded multiprocessors

    Ohmiya, Y. & Amano, H., 2008 Dec 1, Proceedings of the 20th IASTED International Conference on Parallel and Distributed Computing and Systems, PDCS 2008. p. 252-257 6 p. (Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Systems).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • Evaluation of a multicore reconfigurable architecture with variable core sizes

    Tuan, V. M., Katsura, N., Matsutani, H. & Amano, H., 2009 Nov 25, IPDPS 2009 - Proceedings of the 2009 IEEE International Parallel and Distributed Processing Symposium. 5161225. (IPDPS 2009 - Proceedings of the 2009 IEEE International Parallel and Distributed Processing Symposium).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    4 Citations (Scopus)
  • Evaluation of MuCCRA-D: A dynamically reconfigurable processor with directly interconnected PEs

    Kato, M., Hasegawa, Y. & Amano, H., 2008 Dec 1, Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2008. p. 215-221 7 p. (Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2008).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    3 Citations (Scopus)
  • Evaluation of network interface controller on DIMMnet-2 prototype board

    Kitamura, A., Hamada, Y., Miyabe, Y., Izawa, T., Miyashiro, T., Watanabe, K., Otsuka, T., Tanabe, N., Nakajo, H. & Amano, H., 2005 Dec 1, Proceedings - Sixth International Conference on Parallel and Distributed Computing, Applications and Technologies, PDCAT 2005. p. 778-780 3 p. 1579028. (Parallel and Distributed Computing, Applications and Technologies, PDCAT Proceedings; vol. 2005).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    2 Citations (Scopus)
  • Expandable Chip Stacking Method for Many-core Architectures Consisting of Tiny Chips

    Nakahara, H., Ozaki, T., Matsutani, H., Koibuchi, M. & Amano, H., 2015 Nov 11, Proceedings - IEEE 9th International Symposium on Embedded Multicore/Manycore SoCs, MCSoC 2015. Institute of Electrical and Electronics Engineers Inc., p. 41-48 8 p. 7328185

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    1 Citation (Scopus)
  • Exploiting memory hierarchy for a Computational Fluid Dynamics accelerator on FPGAs

    Morishita, H., Osana, Y., Fujita, N. & Amano, H., 2008 Dec 1, Proceedings of the 2008 International Conference on Field-Programmable Technology, ICFPT 2008. p. 193-200 8 p. 4762383. (Proceedings of the 2008 International Conference on Field-Programmable Technology, ICFPT 2008).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    12 Citations (Scopus)
  • Exploiting temporal parallelism in particle-based incompressive fluid simulation on FPGA

    Orsztynowicz, M., Amano, H., Kubota, K. & Miyajima, T., 2020 Nov, Proceedings - 2020 8th International Symposium on Computing and Networking, CANDAR 2020. Institute of Electrical and Electronics Engineers Inc., p. 195-201 7 p. 09394388. (Proceedings - 2020 8th International Symposium on Computing and Networking, CANDAR 2020).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • Exploring the optimal size for multicasting configuration data of dynamically Reconfigurable processors

    Nakamura, T., Sano, T., Hasegawa, Y., Tsutsumi, S., Tunbunheng, V. & Amano, H., 2008 Dec 1, Proceedings of the 2008 International Conference on Field-Programmable Technology, ICFPT 2008. p. 137-144 8 p. 4762376. (Proceedings of the 2008 International Conference on Field-Programmable Technology, ICFPT 2008).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    3 Citations (Scopus)
  • Extension of memory controller equipped with MuCCRA-3-DP: Dynamically reconfigurable processor array

    Katagiri, T., Hironaka, K. & Amano, H., 2012 Dec 14, Proceedings of the 2012 15th International Conference on Network-Based Information Systems, NBIS 2012. p. 826-831 6 p. 6354932. (Proceedings of the 2012 15th International Conference on Network-Based Information Systems, NBIS 2012).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    2 Citations (Scopus)
  • Fined-grained body biasing for frequency scaling in advanced SOI processes

    Kuhn, J. M., Amano, H., Bringmann, O. & Rosenstiel, W., 2015 Jul 14, IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips XVIII - Proceedings. Institute of Electrical and Electronics Engineers Inc., 7158655

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    2 Citations (Scopus)
  • Fine grain partial reconfiguration for energy saving in dynamically reconfigurable processors

    Sano, T., Saito, Y., Kato, M. & Amano, H., 2009 Nov 25, FPL 09: 19th International Conference on Field Programmable Logic and Applications. p. 530-533 4 p. 5272435. (FPL 09: 19th International Conference on Field Programmable Logic and Applications).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    2 Citations (Scopus)
  • Fpga/python co-design for lane line detection on a pynq-z1 board

    Honda, K., Wei, K. & Amano, H., 2019 Oct, Proceedings - 2019 IEEE 13th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019. Institute of Electrical and Electronics Engineers Inc., p. 53-60 8 p. 8906682. (Proceedings - 2019 IEEE 13th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • FPGA Acceleration of ROS2-Based Reinforcement Learning Agents

    Leal, D. P., Sugaya, M., Amano, H. & Ohkawa, T., 2020 Nov, Proceedings - 2020 8th International Symposium on Computing and Networking Workshops, CANDARW 2020. Institute of Electrical and Electronics Engineers Inc., p. 106-112 7 p. 9355892. (Proceedings - 2020 8th International Symposium on Computing and Networking Workshops, CANDARW 2020).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • FPGA-based accelerator for losslessly quantized convolutional neural networks

    Sit, M., Kazami, R. & Amano, H., 2018 Feb 2, 2017 International Conference on Field-Programmable Technology, ICFPT 2017. Institute of Electrical and Electronics Engineers Inc., p. 295-298 4 p. (2017 International Conference on Field-Programmable Technology, ICFPT 2017; vol. 2018-January).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    5 Citations (Scopus)
  • FPGA Design for Autonomous Vehicle Driving Using Binarized Neural Networks

    Wei, K., Honda, K. & Amano, H., 2018 Dec, Proceedings - 2018 International Conference on Field-Programmable Technology, FPT 2018. Institute of Electrical and Electronics Engineers Inc., p. 428-431 4 p. 8742321. (Proceedings - 2018 International Conference on Field-Programmable Technology, FPT 2018).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    3 Citations (Scopus)
  • FPGA implementation of a data-driven stochastic biochemical simulator with the next reaction method

    Yoshimi, M., Iwaoka, Y., Nishikawa, Y., Kojima, T., Osana, Y., Funahashi, A., Hiroi, N., Shibata, Y., Iwanaga, N., Yamada, H., Kitano, H. & Amano, H., 2007, Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL. p. 254-259 6 p. 4380656. (Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    14 Citations (Scopus)
  • FPGA implementation of viscous function in a package for computational fluid dynamics

    Mishra, D., Hatto, M., Kuhara, T., Fujita, N., Osana, Y. & Amano, H., 2015 Feb 27, Proceedings - 2014 2nd International Symposium on Computing and Networking, CANDAR 2014. Institute of Electrical and Electronics Engineers Inc., p. 608-610 3 p. 7052258. (Proceedings - 2014 2nd International Symposium on Computing and Networking, CANDAR 2014).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • From FLOPS to BYTES: Disruptive change in high-performance computing towards the post-moore era

    Matsuoka, S., Amano, H., Nakajima, K., Inoue, K., Kudoh, T., Maruyama, N., Taura, K., Iwashita, T., Katagiri, T., Hanawa, T. & Endo, T., 2016 May 16, 2016 ACM International Conference on Computing Frontiers - Proceedings. Association for Computing Machinery, Inc, p. 274-281 8 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    6 Citations (Scopus)
  • Geyser-1: A MIPS R3000 CPU core with fine-grained run-time power gating

    Ikebuchi, D., Seki, N., Kojima, Y., Kamata, M., Zhao, L., Amano, H., Shirai, T., Koyama, S., Hashida, T., Umahashi, Y., Masuda, H., Usami, K., Takeda, S., Nakamura, H., Namiki, M. & Kondo, M., 2010, 2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010. p. 369-370 2 p. 5419857. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    4 Citations (Scopus)
  • Geyser-1: A MIPS R3000 CPU core with fine grain runtime power gating

    Ikebuchi, D., Seki, N., Kojima, Y., Kamata, M., Zhao, L., Amano, H., Shirai, T., Koyamat, S., Hashida, T., Umahashi, Y., Masuda, H., Usami, K., Takeda, S., Nakamura, H., Namiki, M. & Kondo, M., 2009 Dec 1, Proceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009. p. 281-284 4 p. 5357257. (Proceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    33 Citations (Scopus)
  • Geyser-2: The second prototype CPU with fine-grained run-time power gating

    Zhao, L., Ikebuchi, D., Saito, Y., Kamata, M., Seki, N., Kojima, Y., Amano, H., Koyama, S., Hashida, T., Umahashi, Y., Masuda, D., Usami, K., Kimura, K., Namiki, M., Takeda, S., Nakamura, H. & Kondo, M., 2011 Mar 28, 2011 16th Asia and South Pacific Design Automation Conference, ASP-DAC 2011. p. 87-88 2 p. 5722310. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    11 Citations (Scopus)
  • Glitch-aware variable pipeline optimization for CGRAs

    Kojima, T., Ando, N., Okuhara, H. & Amano, H., 2018 Feb 2, 2017 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2017. Institute of Electrical and Electronics Engineers Inc., Vol. 2018-January. p. 1-6 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    3 Citations (Scopus)
  • Hardware/software co-design architecture for Blokus Duo solver

    Sugimoto, N. & Amano, H., 2014, Proceedings of the 2014 International Conference on Field-Programmable Technology, FPT 2014. Institute of Electrical and Electronics Engineers Inc., p. 358-361 4 p. 7082820

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    4 Citations (Scopus)
  • Hardware support for MPI in DIMMnet-2 network interface

    Tanabe, N., Kitamura, A., Miyashiro, T., Miyabe, Y., Araki, T., Luo, Z., Nakajo, H. & Amano, H., 2006 Dec 1, Proceedings - International Workshop on Innovative Architecture for Future Generation High Performance Processors and Systems, IWIA 2006. p. 73-80 8 p. 4089358. (Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    5 Citations (Scopus)
  • Headfirst sliding routing: A time-based routing scheme for bus-NoC hybrid 3-D architecture

    Kagami, T., Matsutani, H., Koibuchi, M. & Amano, H., 2013, 2013 7th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2013. 6558406. (2013 7th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2013).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    5 Citations (Scopus)
  • High-Bandwidth Low-Latency Approximate Interconnection Networks

    Fujiki, D., Ishii, K., Fujiwara, I., Matsutani, H., Amano, H., Casanova, H. & Koibuchi, M., 2017 May 5, Proceedings - 2017 IEEE 23rd Symposium on High Performance Computer Architecture, HPCA 2017. IEEE Computer Society, p. 469-480 12 p. 7920848

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    13 Citations (Scopus)
  • HiRy: An advanced theory on design of deadlock-free adaptive routing for arbitrary topologies

    Kawano, R., Yasudo, R., Matsutani, H., Koibuchi, M. & Amano, H., 2018 May 29, Proceedings - 2017 IEEE 23rd International Conference on Parallel and Distributed Systems, ICPADS 2017. IEEE Computer Society, p. 664-673 10 p. (Proceedings of the International Conference on Parallel and Distributed Systems - ICPADS; vol. 2017-December).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    2 Citations (Scopus)
  • HOBONET: AN INTER-PU CONNECTION NETWORK WITH FAULT-TOLERANCY.

    Osawa, G., Yokota, T., Amano, H. & Aiso, H., 1984 Dec 1, Proceedings of the International Conference on Parallel Processing. Keller, R. M. (ed.). IEEE, p. 165-168 4 p. (Proceedings of the International Conference on Parallel Processing).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • Horizontal division of deep learning applications with all-to-all communication on a multi-FPGA system

    Yamauchi, Y., Ahmed, A. B., Hironaka, K., Iizuka, K. & Amano, H., 2020 Nov, Proceedings - 2020 8th International Symposium on Computing and Networking Workshops, CANDARW 2020. Institute of Electrical and Electronics Engineers Inc., p. 277-281 5 p. 9355950. (Proceedings - 2020 8th International Symposium on Computing and Networking Workshops, CANDARW 2020).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    2 Citations (Scopus)
  • HOSMII: A virtual hardware integrated with DRAM

    Shibata, Y., Miyazaki, H., Ling, X. P. & Amano, H., 1998, Parallel and Distributed Processing - 10 IPPS/SPDP 1998 Workshops Held in Conjunction with the 12th International Parallel Processing Symposium and 9th Symposium on Parallel and Distributed Processing, Proceedings. Rolim, J. (ed.). Springer Verlag, p. 85-90 6 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 1388).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    1 Citation (Scopus)
  • Hybrid Network of Packet Switching and STDM in a Multi-FPGA System

    Shimizu, T., Ito, K., Iizuka, K., Hironaka, K. & Amano, H., 2021 Apr 14, IEEE Symposium in Low-Power and High-Speed Chips, COOL CHIPS 2021 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 9410322. (IEEE Symposium in Low-Power and High-Speed Chips, COOL CHIPS 2021 - Proceedings).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    1 Citation (Scopus)
  • Image processing by A 0.3V 2MW coarse-grained reconfigurable accelerator CMA-SOTB with a solar battery

    Fujita, Y., Masuyama, K. & Amano, H., 2015 Apr 8, Proceedings of the 2014 International Conference on Field-Programmable Technology, FPT 2014. Chen, J., Shibata, Y., Wang, L., So, H. K-H., Ma, Y. & Yin, W. (eds.). Institute of Electrical and Electronics Engineers Inc., p. 354-357 4 p. 7082818. (Proceedings of the 2014 International Conference on Field-Programmable Technology, FPT 2014).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    1 Citation (Scopus)
  • Implementation and evaluation of a high speed license plate recognition system on an FPGA

    Kanamori, T., Amano, H., Arai, M., Konno, D., Nanba, T. & Ajioka, Y., 2007, CIT 2007: 7th IEEE International Conference on Computer and Information Technology. p. 567-572 6 p. 4385143. (CIT 2007: 7th IEEE International Conference on Computer and Information Technology).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    9 Citations (Scopus)
  • Implementation and evaluation of fine-grain run-time power gating for a multiplier

    Usami, K., Nakata, M., Shirai, T., Takeda, S., Seki, N., Amano, H. & Nakamura, H., 2009 Dec 1, 2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009. p. 7-10 4 p. 5166253. (2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    7 Citations (Scopus)
  • Implementation and evaluation of self-organizing map algorithm on a graphic processor

    Shitara, A., Nishikawa, Y., Yoshimi, M. & Amano, H., 2009 Dec 1, Proceedings of the 21st IASTED International Conference on Parallel and Distributed Computing and Systems, PDCS 2009. p. 253-260 8 p. (Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Systems).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    2 Citations (Scopus)
  • Implementation and evaluation of the compiler for WASMII, a virtual hardware system

    Takayama, A., Shibata, Y., Iwai, K., Miyazaki, H., Higure, K., Ling, X. P. & Amano, H., 1999, Proceedings - 1999 lnternational Workshops on Parallel Processing, ICPP 1999. Institute of Electrical and Electronics Engineers Inc., p. 346-351 6 p. 800084. (Proceedings of the International Conference on Parallel Processing; vol. 1999-September).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    4 Citations (Scopus)
  • Implementation and evaluation of the mechanisms for low latency communication on DIMMnet-2

    Miyabe, Y., Kitamura, A., Hamada, Y., Miyasiro, T., Izawa, T., Tanabe, N., Nakajo, H. & Amano, H., 2008, High-Performance Computing - 6th International Symposium, ISHPC 2005 and First International Workshop on Advanced Low Power Systems, ALPS 2006, Revised Selected Papers. Springer Verlag, p. 211-218 8 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 4759 LNCS).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • Implementation of active direction-pass filter on dynamically reconfigurable processor

    Kurotaki, S., Suzuki, N., Nakadai, K., Okuno, H. G. & Amano, H., 2005, 2005 IEEE/RSJ International Conference on Intelligent Robots and Systems, IROS. IEEE Computer Society, p. 3175-3180 6 p. 1545033. (2005 IEEE/RSJ International Conference on Intelligent Robots and Systems, IROS).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    7 Citations (Scopus)
  • Implementation of bitsliced AES encryption on CUDA-Enabled GPU

    Nishikawa, N., Amano, H. & Iwai, K., 2017, Network and System Security - 11th International Conference, NSS 2017, Proceedings. Springer Verlag, Vol. 10394 LNCS. p. 273-287 15 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 10394 LNCS).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    13 Citations (Scopus)
  • Implementation of FM-Index Based Pattern Search on a Multi-FPGA System

    Ullah, M. M. I., Ben Ahmed, A. & Amano, H., 2020, Applied Reconfigurable Computing. Architectures, Tools, and Applications - 16th International Symposium, ARC 2020, Proceedings. Rincón, F., Barba, J., Caba, J., So, H. K. H. & Diniz, P. (eds.). Springer, p. 376-391 16 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 12083 LNCS).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    1 Citation (Scopus)
  • Implementation of ISIS-simplescalar

    Hanawa, T., Minai, T., Tanabe, Y. & Amano, H., 2005 Dec 1, Proceedings of the 2005 International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA'05. p. 117-123 7 p. (Proceedings of the 2005 International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA'05; vol. 1).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • Implementing a large application(LSTM) on the multi-FPGA system: Flow-in-Cloud

    Yamauchi, Y., Musha, K. & Amano, H., 2019 May 23, IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2019 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 8721333. (IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2019 - Proceedings).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    2 Citations (Scopus)
  • Implementing a Multi-ejection Switch and Making the Use of Multiple Lanes in a Circuit-switched Multi-FPGA System

    Ito, K., Iizuka, K., Hironaka, K., Hu, Y., Koibuchi, M. & Amano, H., 2020 Nov, Proceedings - 2020 8th International Symposium on Computing and Networking Workshops, CANDARW 2020. Institute of Electrical and Electronics Engineers Inc., p. 211-217 7 p. 9355926. (Proceedings - 2020 8th International Symposium on Computing and Networking Workshops, CANDARW 2020).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    3 Citations (Scopus)
  • Implementing and evaluating stream applications on the dynamically reconfigurable processor

    Suzuki, N., Kurotaki, S., Suzuki, M., Kaneko, N., Yamada, Y., Deguchi, K., Hasegawa, Y., Amano, H., Anjo, K., Motomura, M., Wakabayashi, K., Toi, T. & Awashima, T., 2004 Dec 1, Proceedings - 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2004. Arnold, J. & Pocek, K. L. (eds.). p. 328-329 2 p. (Proceedings - 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2004).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    12 Citations (Scopus)
  • Implementing breadth-first search on a compact supercomputer suiren

    Mitsuishi, T., Kaneda, T., Torii, S. & Amano, H., 2017 Jan 13, Proceedings - 2016 4th International Symposium on Computing and Networking, CANDAR 2016. Institute of Electrical and Electronics Engineers Inc., p. 395-401 7 p. 7818645

    Research output: Chapter in Book/Report/Conference proceedingConference contribution