• 2531 Citations
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1983 …2020

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Evaluation of network interface controller on DIMMnet-2 prototype board

Kitamura, A., Hamada, Y., Miyabe, Y., Izawa, T., Miyashiro, T., Watanabe, K., Otsuka, T., Tanabe, N., Nakajo, H. & Amano, H., 2005 Dec 1, Proceedings - Sixth International Conference on Parallel and Distributed Computing, Applications and Technologies, PDCAT 2005. p. 778-780 3 p. 1579028. (Parallel and Distributed Computing, Applications and Technologies, PDCAT Proceedings; vol. 2005).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Expandable Chip Stacking Method for Many-core Architectures Consisting of Tiny Chips

Nakahara, H., Ozaki, T., Matsutani, H., Koibuchi, M. & Amano, H., 2015 Nov 11, Proceedings - IEEE 9th International Symposium on Embedded Multicore/Manycore SoCs, MCSoC 2015. Institute of Electrical and Electronics Engineers Inc., p. 41-48 8 p. 7328185

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Exploiting memory hierarchy for a Computational Fluid Dynamics accelerator on FPGAs

Morishita, H., Osana, Y., Fujita, N. & Amano, H., 2008 Dec 1, Proceedings of the 2008 International Conference on Field-Programmable Technology, ICFPT 2008. p. 193-200 8 p. 4762383. (Proceedings of the 2008 International Conference on Field-Programmable Technology, ICFPT 2008).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Citations (Scopus)

Exploring the optimal size for multicasting configuration data of dynamically Reconfigurable processors

Nakamura, T., Sano, T., Hasegawa, Y., Tsutsumi, S., Tunbunheng, V. & Amano, H., 2008 Dec 1, Proceedings of the 2008 International Conference on Field-Programmable Technology, ICFPT 2008. p. 137-144 8 p. 4762376. (Proceedings of the 2008 International Conference on Field-Programmable Technology, ICFPT 2008).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Extension of memory controller equipped with MuCCRA-3-DP: Dynamically reconfigurable processor array

Katagiri, T., Hironaka, K. & Amano, H., 2012 Dec 14, Proceedings of the 2012 15th International Conference on Network-Based Information Systems, NBIS 2012. p. 826-831 6 p. 6354932. (Proceedings of the 2012 15th International Conference on Network-Based Information Systems, NBIS 2012).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Fined-grained body biasing for frequency scaling in advanced SOI processes

Kuhn, J. M., Amano, H., Bringmann, O. & Rosenstiel, W., 2015 Jul 14, IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips XVIII - Proceedings. Institute of Electrical and Electronics Engineers Inc., 7158655

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Fine grain partial reconfiguration for energy saving in dynamically reconfigurable processors

Sano, T., Saito, Y., Kato, M. & Amano, H., 2009 Nov 25, FPL 09: 19th International Conference on Field Programmable Logic and Applications. p. 530-533 4 p. 5272435. (FPL 09: 19th International Conference on Field Programmable Logic and Applications).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Fpga/python co-design for lane line detection on a pynq-z1 board

Honda, K., Wei, K. & Amano, H., 2019 Oct, Proceedings - 2019 IEEE 13th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019. Institute of Electrical and Electronics Engineers Inc., p. 53-60 8 p. 8906682. (Proceedings - 2019 IEEE 13th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

FPGA-based accelerator for losslessly quantized convolutional neural networks

Sit, M., Kazami, R. & Amano, H., 2018 Feb 2, 2017 International Conference on Field-Programmable Technology, ICFPT 2017. Institute of Electrical and Electronics Engineers Inc., Vol. 2018-January. p. 295-298 4 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

FPGA Design for Autonomous Vehicle Driving Using Binarized Neural Networks

Wei, K., Honda, K. & Amano, H., 2018 Dec, Proceedings - 2018 International Conference on Field-Programmable Technology, FPT 2018. Institute of Electrical and Electronics Engineers Inc., p. 428-431 4 p. 8742321. (Proceedings - 2018 International Conference on Field-Programmable Technology, FPT 2018).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

FPGA implementation of a data-driven stochastic biochemical simulator with the next reaction method

Yoshimi, M., Iwaoka, Y., Nishikawa, Y., Kojima, T., Osana, Y., Funahashi, A., Hiroi, N., Shibata, Y., Iwanaga, N., Yamada, H., Kitano, H. & Amano, H., 2007 Dec 1, Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL. p. 254-259 6 p. 4380656. (Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

14 Citations (Scopus)

FPGA implementation of viscous function in a package for computational fluid dynamics

Mishra, D., Hatto, M., Kuhara, T., Fujita, N., Osana, Y. & Amano, H., 2015 Feb 27, Proceedings - 2014 2nd International Symposium on Computing and Networking, CANDAR 2014. Institute of Electrical and Electronics Engineers Inc., p. 608-610 3 p. 7052258. (Proceedings - 2014 2nd International Symposium on Computing and Networking, CANDAR 2014).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

From FLOPS to BYTES: Disruptive change in high-performance computing towards the post-moore era

Matsuoka, S., Amano, H., Nakajima, K., Inoue, K., Kudoh, T., Maruyama, N., Taura, K., Iwashita, T., Katagiri, T., Hanawa, T. & Endo, T., 2016 May 16, 2016 ACM International Conference on Computing Frontiers - Proceedings. Association for Computing Machinery, Inc, p. 274-281 8 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Geyser-1: A MIPS R3000 CPU core with fine-grained run-time power gating

Ikebuchi, D., Seki, N., Kojima, Y., Kamata, M., Zhao, L., Amano, H., Shirai, T., Koyama, S., Hashida, T., Umahashi, Y., Masuda, H., Usami, K., Takeda, S., Nakamura, H., Namiki, M. & Kondo, M., 2010 Apr 28, 2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010. p. 369-370 2 p. 5419857. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Geyser-1: A MIPS R3000 CPU core with fine grain runtime power gating

Ikebuchi, D., Seki, N., Kojima, Y., Kamata, M., Zhao, L., Amano, H., Shirai, T., Koyamat, S., Hashida, T., Umahashi, Y., Masuda, H., Usami, K., Takeda, S., Nakamura, H., Namiki, M. & Kondo, M., 2009 Dec 1, Proceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009. p. 281-284 4 p. 5357257. (Proceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

33 Citations (Scopus)

Geyser-2: The second prototype CPU with fine-grained run-time power gating

Zhao, L., Ikebuchi, D., Saito, Y., Kamata, M., Seki, N., Kojima, Y., Amano, H., Koyama, S., Hashida, T., Umahashi, Y., Masuda, D., Usami, K., Kimura, K., Namiki, M., Takeda, S., Nakamura, H. & Kondo, M., 2011 Mar 28, 2011 16th Asia and South Pacific Design Automation Conference, ASP-DAC 2011. p. 87-88 2 p. 5722310. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Citations (Scopus)

Glitch-aware variable pipeline optimization for CGRAs

Kojima, T., Ando, N., Okuhara, H. & Amano, H., 2018 Feb 2, 2017 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2017. Institute of Electrical and Electronics Engineers Inc., Vol. 2018-January. p. 1-6 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Hardware/software co-design architecture for Blokus Duo solver

Sugimoto, N. & Amano, H., 2014, Proceedings of the 2014 International Conference on Field-Programmable Technology, FPT 2014. Institute of Electrical and Electronics Engineers Inc., p. 358-361 4 p. 7082820

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Hardware support for MPI in DIMMnet-2 network interface

Tanabe, N., Kitamura, A., Miyashiro, T., Miyabe, Y., Araki, T., Luo, Z., Nakajo, H. & Amano, H., 2006 Dec 1, Proceedings - International Workshop on Innovative Architecture for Future Generation High Performance Processors and Systems, IWIA 2006. p. 73-80 8 p. 4089358. (Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Headfirst sliding routing: A time-based routing scheme for bus-NoC hybrid 3-D architecture

Kagami, T., Matsutani, H., Koibuchi, M. & Amano, H., 2013 Aug 19, 2013 7th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2013. 6558406. (2013 7th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2013).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

High-Bandwidth Low-Latency Approximate Interconnection Networks

Fujiki, D., Ishii, K., Fujiwara, I., Matsutani, H., Amano, H., Casanova, H. & Koibuchi, M., 2017 May 5, Proceedings - 2017 IEEE 23rd Symposium on High Performance Computer Architecture, HPCA 2017. IEEE Computer Society, p. 469-480 12 p. 7920848

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Citations (Scopus)

HiRy: An advanced theory on design of deadlock-free adaptive routing for arbitrary topologies

Kawano, R., Yasudo, R., Matsutani, H., Koibuchi, M. & Amano, H., 2018 May 29, Proceedings - 2017 IEEE 23rd International Conference on Parallel and Distributed Systems, ICPADS 2017. IEEE Computer Society, Vol. 2017-December. p. 664-673 10 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

HOBONET: AN INTER-PU CONNECTION NETWORK WITH FAULT-TOLERANCY.

Osawa, G., Yokota, T., Amano, H. & Aiso, H., 1984 Dec 1, Proceedings of the International Conference on Parallel Processing. Keller, R. M. (ed.). IEEE, p. 165-168 4 p. (Proceedings of the International Conference on Parallel Processing).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

HOSMII: A virtual hardware integrated with DRAM

Shibata, Y., Miyazaki, H., Ling, X. P. & Amano, H., 1998, Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Springer Verlag, Vol. 1388. p. 85-90 6 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 1388).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Image processing by A 0.3V 2MW coarse-grained reconfigurable accelerator CMA-SOTB with a solar battery

Fujita, Y., Masuyama, K. & Amano, H., 2015 Apr 8, Proceedings of the 2014 International Conference on Field-Programmable Technology, FPT 2014. Chen, J., Shibata, Y., Wang, L., So, H. K-H., Ma, Y. & Yin, W. (eds.). Institute of Electrical and Electronics Engineers Inc., p. 354-357 4 p. 7082818. (Proceedings of the 2014 International Conference on Field-Programmable Technology, FPT 2014).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Implementation and evaluation of a high speed license plate recognition system on an FPGA

Kanamori, T., Amano, H., Arai, M., Konno, D., Nanba, T. & Ajioka, Y., 2007 Dec 1, CIT 2007: 7th IEEE International Conference on Computer and Information Technology. p. 567-572 6 p. 4385143. (CIT 2007: 7th IEEE International Conference on Computer and Information Technology).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Citations (Scopus)

Implementation and evaluation of fine-grain run-time power gating for a multiplier

Usami, K., Nakata, M., Shirai, T., Takeda, S., Seki, N., Amano, H. & Nakamura, H., 2009 Dec 1, 2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009. p. 7-10 4 p. 5166253. (2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Implementation and evaluation of self-organizing map algorithm on a graphic processor

Shitara, A., Nishikawa, Y., Yoshimi, M. & Amano, H., 2009 Dec 1, Proceedings of the 21st IASTED International Conference on Parallel and Distributed Computing and Systems, PDCS 2009. p. 253-260 8 p. (Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Systems).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Implementation and evaluation of the compiler for WASMII, a virtual hardware system

Takayama, A., Shibata, Y., Iwai, K., Miyazaki, H., Higure, K., Ling, X. P. & Amano, H., 1999 Jan 1, Proceedings - 1999 lnternational Workshops on Parallel Processing, ICPP 1999. Institute of Electrical and Electronics Engineers Inc., p. 346-351 6 p. 800084. (Proceedings of the International Conference on Parallel Processing; vol. 1999-September).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Implementation and evaluation of the mechanisms for low latency communication on DIMMnet-2

Miyabe, Y., Kitamura, A., Hamada, Y., Miyasiro, T., Izawa, T., Tanabe, N., Nakajo, H. & Amano, H., 2008 Feb 1, High-Performance Computing - 6th International Symposium, ISHPC 2005 and First International Workshop on Advanced Low Power Systems, ALPS 2006, Revised Selected Papers. p. 211-218 8 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 4759 LNCS).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Implementation of active direction-pass filter on dynamically reconfigurable processor

Kurotaki, S., Suzuki, N., Nakadai, K., Okuno, H. G. & Amano, H., 2005 Dec 1, 2005 IEEE/RSJ International Conference on Intelligent Robots and Systems, IROS. p. 515-520 6 p. 1545033. (2005 IEEE/RSJ International Conference on Intelligent Robots and Systems, IROS).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Implementation of bitsliced AES encryption on CUDA-Enabled GPU

Nishikawa, N., Amano, H. & Iwai, K., 2017, Network and System Security - 11th International Conference, NSS 2017, Proceedings. Springer Verlag, Vol. 10394 LNCS. p. 273-287 15 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 10394 LNCS).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Implementation of FM-Index Based Pattern Search on a Multi-FPGA System

Ullah, M. M. I., Ben Ahmed, A. & Amano, H., 2020 Jan 1, Applied Reconfigurable Computing. Architectures, Tools, and Applications - 16th International Symposium, ARC 2020, Proceedings. Rincón, F., Barba, J., Caba, J., So, H. K. H. & Diniz, P. (eds.). Springer, p. 376-391 16 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 12083 LNCS).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Implementation of ISIS-simplescalar

Hanawa, T., Minai, T., Tanabe, Y. & Amano, H., 2005 Dec 1, Proceedings of the 2005 International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA'05. p. 117-123 7 p. (Proceedings of the 2005 International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA'05; vol. 1).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Implementing a large application(LSTM) on the multi-FPGA system: Flow-in-Cloud

Yamauchi, Y., Musha, K. & Amano, H., 2019 May 23, IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2019 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 8721333. (IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2019 - Proceedings).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Implementing and evaluating stream applications on the dynamically reconfigurable processor

Suzuki, N., Kurotaki, S., Suzuki, M., Kaneko, N., Yamada, Y., Deguchi, K., Hasegawa, Y., Amano, H., Anjo, K., Motomura, M., Wakabayashi, K., Toi, T. & Awashima, T., 2004 Dec 1, Proceedings - 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2004. Arnold, J. & Pocek, K. L. (eds.). p. 328-329 2 p. (Proceedings - 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2004).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Citations (Scopus)

Implementing breadth-first search on a compact supercomputer suiren

Mitsuishi, T., Kaneda, T., Torii, S. & Amano, H., 2017 Jan 13, Proceedings - 2016 4th International Symposium on Computing and Networking, CANDAR 2016. Institute of Electrical and Electronics Engineers Inc., p. 395-401 7 p. 7818645

Research output: Chapter in Book/Report/Conference proceedingConference contribution

IMPULSE: A HIGH PERFORMANCE PROCESSING UNIT FOR MULTIPROCESSORS FOR SCIENTIFIC CALCULATION.

Boku, T., Nomura, S. & Amano, H., 1988 Jan 1, Unknown Host Publication Title. IEEE, p. 365-372 8 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Instruction buffer mode for multi-context dynamically reconfigurable processors

Sano, T., Kato, M., Tsutsumi, S., Hasegawa, Y. & Amano, H., 2008 Nov 3, Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL. p. 215-220 6 p. 4629934. (Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

In-switch approximate processing: Delayed tasks management for MapReduce applications

Mitsuzuka, K., Hayashi, A., Koibuchi, M., Amano, H. & Matsutani, H., 2017 Oct 2, 2017 27th International Conference on Field Programmable Logic and Applications, FPL 2017. Institute of Electrical and Electronics Engineers Inc., 8056802

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Internal parallelization of data-driven virtual hardware

Shibata, Y., Ling, X. P. & Amano, H., 1999 Jan 1, Proceedings - 1999 lnternational Workshops on Parallel Processing, ICPP 1999. Institute of Electrical and Electronics Engineers Inc., Vol. 1999-September. p. 366-371 6 p. 800087

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Key-value Store Chip Design for Low Power Consumption

Tokusashi, Y., Matsutani, H. & Amano, H., 2019 May 23, IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2019 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 8721352. (IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2019 - Proceedings).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

K-Optimized Path Routing for High-Throughput Data Center Networks

Kawano, R., Yasudo, R., Matsutani, H. & Amano, H., 2018 Dec 27, Proceedings - 2018 6th International Symposium on Computing and Networking, CANDAR 2018. Institute of Electrical and Electronics Engineers Inc., p. 99-105 7 p. 8594749. (Proceedings - 2018 6th International Symposium on Computing and Networking, CANDAR 2018).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Leakage power reduction for coarse-grained dynamically reconfigurable processor arrays using dual Vt cells

Hirai, K., Kato, M., Saito, Y. & Amano, H., 2009 Dec 1, Proceedings of the 2009 International Conference on Field-Programmable Technology, FPT'09. p. 104-111 8 p. 5377641. (Proceedings of the 2009 International Conference on Field-Programmable Technology, FPT'09).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Leakage power Reduction for coarse grained dynamically reconfigurable processor arrays with fine grained power Gating technique

Saito, Y., Shirai, T., Nakamura, T., Nishimura, T., Hasegawa, Y., Tsutsumi, S., Kashima, T., Nakata, M., Takeda, S., Usami, K. & Amano, H., 2008 Dec 1, Proceedings of the 2008 International Conference on Field-Programmable Technology, ICFPT 2008. p. 329-332 4 p. 4762410. (Proceedings of the 2008 International Conference on Field-Programmable Technology, ICFPT 2008).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

15 Citations (Scopus)

Level-shifter free approach for multi-Vdd SOTB employing adaptive Vt modulation for pMOSFET

Usami, K., Kogure, S., Yoshida, Y., Magasaki, R. & Amano, H., 2018 Mar 7, 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017. Institute of Electrical and Electronics Engineers Inc., Vol. 2018-March. p. 1-3 3 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Level-shifter-less approach for multi-VDD design to use body bias control in FD-SOI

Usami, K., Kogure, S., Yoshida, Y., Magasaki, R. & Amano, H., 2017 Dec 13, 25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017 - Proceedings. IEEE Computer Society, 8203473

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Level-Shifter-Less Approach for Multi-VDD SoC Design to Employ Body Bias Control in FD-SOI

Usami, K., Kogure, S., Yoshida, Y., Magasaki, R. & Amano, H., 2019 Jan 1, VLSI-SoC: Opportunities and Challenges Beyond the Internet of Things - 25th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017, Revised and Extended Selected Papers. Monteiro, J., Elfadel, I. A. M., Sonza Reorda, M., Ugurdag, H. F., Maniatakos, M. & Reis, R. (eds.). Springer New York LLC, p. 1-21 21 p. (IFIP Advances in Information and Communication Technology; vol. 500).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Leveraging asymmetric body bias control for low power LSI design

Okuhara, H., Ahmed, A. B., Kuhn, J. M. & Amano, H., 2017 Jun 12, Proceedings for 2017 IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips 2017. Institute of Electrical and Electronics Engineers Inc., 7946379

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Leveraging FDSOI through body bias domain partitioning and bias search

Kühn, J. M., Amano, H., Bringmann, O. & Rosenstiel, W., 2016 Jun 5, Proceedings of the 53rd Annual Design Automation Conference, DAC 2016. Institute of Electrical and Electronics Engineers Inc., Vol. 05-09-June-2016. a79

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)