• 2531 Citations
  • 23 h-Index
1983 …2020

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LOREN: A scalable routing method for layout-conscious random topologies

Kawano, R., Nakahara, H., Fujiwara, I., Matsutani, H., Koibuchi, M. & Amano, H., 2017 Jan 13, Proceedings - 2016 4th International Symposium on Computing and Networking, CANDAR 2016. Institute of Electrical and Electronics Engineers Inc., p. 9-18 10 p. 7818589

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Low-latency wireless 3D NoCs via randomized shortcut chips

Matsutani, H., Koibuchi, M., Fujiwara, I., Kagami, T., Take, Y., Kuroda, T., Bogdan, P., Marculescu, R. & Amano, H., 2014 Jan 1, Proceedings - Design, Automation and Test in Europe, DATE 2014. Institute of Electrical and Electronics Engineers Inc., 6800487. (Proceedings -Design, Automation and Test in Europe, DATE).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

32 Citations (Scopus)

Low power image processing using MuCCRA-3: A dynamically reconfigurable processor array

Kimura, M., Saito, Y., Sano, T., Kato, M., Tunbunheng, V., Yasuda, Y. & Amano, H., 2009 Dec 1, Proceedings of the 2009 International Conference on Field-Programmable Technology, FPT'09. p. 364-367 4 p. 5377614. (Proceedings of the 2009 International Conference on Field-Programmable Technology, FPT'09).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

L-turn routing: An adaptive routing in irregular networks

Koibuchi, M., Funahashi, A., Jouraku, A. & Amano, H., 2001, Proceedings of the International Conference on Parallel Processing. Institute of Electrical and Electronics Engineers Inc., Vol. 2001-January. p. 383-392 10 p. 952084

Research output: Chapter in Book/Report/Conference proceedingConference contribution

48 Citations (Scopus)

MAPLE chip: A processing element for a static scheduling centric multiprocessor

Yasufuku, K., Ogawa, R., Iwai, K. & Amano, H., 2003, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Institute of Electrical and Electronics Engineers Inc., Vol. 2003-January. p. 575-576 2 p. 1195085

Research output: Chapter in Book/Report/Conference proceedingConference contribution

MCMA: A modular processing elements array based low-power coarse-grained reconfigurable accelerator

Chaintreuil, R., Uno, R. & Amano, H., 2013 Jan 1, 2013 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2013. IEEE Computer Society, 6732308. (2013 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2013).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

MEMOnet: Network interface plugged into a memory slot

Tanabe, N., Yamamoto, J., Nishi, H., Kudoh, T., Hamada, Y., Nakajo, H. & Amano, H., 2000 Jan 1, Proceedings - IEEE International Conference on Cluster Computing, CLUSTER 2000. Institute of Electrical and Electronics Engineers Inc., p. 17-26 10 p. 888988. (Proceedings - IEEE International Conference on Cluster Computing, ICCC; vol. 2000-January).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

19 Citations (Scopus)

Message from the technical program co-chairs

Amano, H. & Ye, A., 2007 Dec 1, ICFPT 2007 - International Conference on Field Programmable Technology. p. v 4439219. (ICFPT 2007 - International Conference on Field Programmable Technology).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Modularizing flux limiter functions for a computational fluid dynamics accelerator on FPGAS

Inakagata, K., Morishita, H., Osana, Y., Fujita, N. & Amano, H., 2009 Nov 25, FPL 09: 19th International Conference on Field Programmable Logic and Applications. p. 654-657 4 p. 5272347. (FPL 09: 19th International Conference on Field Programmable Logic and Applications).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

MuCCRA-3: A low power dynamically reconfigurable processor array

Saito, Y., Sano, T., Kato, M., Tunbunheng, V., Yasuda, Y., Kimura, M. & Amano, H., 2010 Apr 28, 2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010. p. 377-378 2 p. 5419853. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

MuCCRA4-BB: A fine-grained body biasing capable DRP

Kuhn, J. M., Ben Ahmed, A., Okuhara, H., Amano, H., Bringmann, O. & Rosenstiel, W., 2016 Jul 5, 19th IEEE Symposium on Low-Power and High-Speed Chips, IEEE COOL Chips 2016 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 7503676

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

MuCCRA chips: Configurable dynamically-reconfigurable processors

Amano, H., Hasegawa, Y., Tsutsumi, S., Nakamura, T., Nishimura, T., Tanbunheng, V., Parimala, A., Sano, T. & Kato, M., 2007 Dec 1, 2007 IEEE Asian Solid-State Circuits Conference, A-SSCC. p. 384-387 4 p. 4425711. (2007 IEEE Asian Solid-State Circuits Conference, A-SSCC).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

41 Citations (Scopus)

MuCCRA-Cube: A 3D dynamically reconfigurable processor with inductive-coupling link

Saito, S., Kohama, Y., Sugimori, Y., Hasegawa, Y., Matsutani, H., Sano, T., Kasuga, K., Yoshida, Y., Niitsu, K., Miura, N., Kuroda, T. & Amano, H., 2009 Nov 25, FPL 09: 19th International Conference on Field Programmable Logic and Applications. p. 6-11 6 p. 5272565. (FPL 09: 19th International Conference on Field Programmable Logic and Applications).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

21 Citations (Scopus)

Multi-FPGA Management on Flow-in-Cloud Prototype System

Hironaka, K., Akram, B. A. & Amano, H., 2019 Jul, Proceedings - 20th IEEE/ACIS International Conference on Software Engineering, Artificial Intelligence, Networking and Parallel/Distributed Computing, SNPD 2019. Nakamura, M., Hirata, H., Ito, T., Otsuka, T. & Okuhara, S. (eds.). Institute of Electrical and Electronics Engineers Inc., p. 443-448 6 p. 8935738. (Proceedings - 20th IEEE/ACIS International Conference on Software Engineering, Artificial Intelligence, Networking and Parallel/Distributed Computing, SNPD 2019).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Multi-objective optimization for application mapping and body bias control on a CGRA

Doan, N. A. V., Matsushita, Y., Ando, N., Okuhara, H. & Amano, H., 2018 Mar 26, Proceedings - IEEE 11th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2017. Institute of Electrical and Electronics Engineers Inc., Vol. 2018-January. p. 143-150 8 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Multistage interconnection networks with multiple outlets

Hanawa, T., Amano, H. & Fujikawa, Y., 1994 Jan 1, Proceedings of the 1994 International Conference on Parallel Processing, ICPP 1994. Institute of Electrical and Electronics Engineers Inc., p. I1-I8 4115682. (Proceedings of the International Conference on Parallel Processing; vol. 1).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

14 Citations (Scopus)

Namacha: A software development environment for a multi-chip convolutional network accelerator

Ohkubo, T., Takata, R., Sakamoto, R., Kondo, M. & Amano, H., 2017, Proceedings of the 32nd International Conference on Computers and Their Applications, CATA 2017. The International Society for Computers and Their Applications (ISCA), p. 101-106 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

NDL: A LANGUAGE FOR SOLVING SCIENTIFIC PROBLEMS ON MIMD MACHINES.

Kudoh, T., Amano, H., Boku, T. & Aiso, H., 1985 Dec 1, Unknown Host Publication Title. IEEE, p. 55-64 10 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

On-chip decentralized routers with balanced pipelines for avoiding interconnect bottleneck

Yasudo, R., Matsutani, H., Koibuchi, M., Amano, H. & Nakamura, T., 2015 Sep 28, Proceedings - 2015 9th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2015. Association for Computing Machinery, Inc, 2817280

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

On-chip detection methodology for break-even time of power gated function units

Usami, K., Goto, Y., Matsunaga, K., Koyama, S., Ikebuchi, D., Amano, H. & Nakamura, H., 2011 Sep 19, IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011. p. 241-246 6 p. 5993643. (Proceedings of the International Symposium on Low Power Electronics and Design).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

13 Citations (Scopus)

On-the-fly data compression/decompression mechanism with ExpEther

Shimura, H., Mitsuishi, T., Amano, H., Kan, M. & Yoshikawa, T., 2017 Jan 13, Proceedings - 2016 4th International Symposium on Computing and Networking, CANDAR 2016. Institute of Electrical and Electronics Engineers Inc., p. 112-118 7 p. 7818601

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Optimized core-links for low-latency NoCs

Kawano, R., Tade, S., Fujiwara, I., Matsutani, H., Amano, H. & Koibuchi, M., 2015, Proceedings - 23rd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2015. Institute of Electrical and Electronics Engineers Inc., p. 172-176 5 p. 7092716

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Order/Radix Problem: Towards Low End-to-End Latency Interconnection Networks

Yasudo, R., Koibuchi, M., Nakano, K., Matsutani, H. & Amano, H., 2017 Sep 1, Proceedings - 46th International Conference on Parallel Processing, ICPP 2017. Institute of Electrical and Electronics Engineers Inc., p. 322-331 10 p. 8025306

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Overwrite configuration technique in multicast configuration scheme for dynamically reconfigurable processor arrays

Tsutsumi, S., Tunbunheng, V., Hasegawa, Y., Parimala, A., Nakamura, T., Nishimura, T. & Amano, H., 2007 Dec 1, ICFPT 2007 - International Conference on Field Programmable Technology. p. 273-276 4 p. 4439264. (ICFPT 2007 - International Conference on Field Programmable Technology).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Partially reconfigurable flux calculation scheme in advection term computation

Talip, M. S. A., Akamine, T., Hatto, M., Osana, Y., Fujita, N. & Amano, H., 2013 Dec 1, FPT 2013 - Proceedings of the 2013 International Conference on Field Programmable Technology. p. 382-385 4 p. 6718393. (FPT 2013 - Proceedings of the 2013 International Conference on Field Programmable Technology).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Performance, cost, and energy evaluation of fat H-tree: A cost-efficient tree-based on-chip network

Matsutani, H., Koibuchi, M. & Amano, H., 2007 Sep 24, Proceedings - 21st International Parallel and Distributed Processing Symposium, IPDPS 2007; Abstracts and CD-ROM. 4227999. (Proceedings - 21st International Parallel and Distributed Processing Symposium, IPDPS 2007; Abstracts and CD-ROM).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

18 Citations (Scopus)

Performance, cost, and power evaluations of on-chip network topologies in FPGAs

In, S., Matsutani, H., Koibuchi, M., Wang, D. & Amano, H., 2010 Jul 20, Proceedings of the 9th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2010. p. 181-189 9 p. (Proceedings of the 9th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2010).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Performance/cost trade-off evaluation for the DCT implementation on the dynamically reconfigurable processor

Tuan, V. M., Hasegawa, Y., Katsura, N. & Amano, H., 2006 Jan 1, Reconfigurable Computing: Architectures and Applications - Second International Workshop, ARC 2006, Revised Selected Papers. Springer Verlag, p. 115-121 7 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 3985 LNCS).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Performance analysis for the arbitor of IEEE standard backplane bus Futurebus/Futurebus+

Yamamoto, O., Takemoto, T., Kimura, T. & Amano, H., 1993 Jan 1, Proc IEEE 1993 Pac Rim Conf Commun Comput Signal Process. Publ by IEEE, p. 386-389 4 p. (Proc IEEE 1993 Pac Rim Conf Commun Comput Signal Process).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Performance analysis of clearspeed's CSX600 interconnects

Nishikawa, Y., Koibuchi, M., Yoshimi, M., Shitara, A., Miura, K. & Amano, H., 2009 Nov 19, Proceedings - 2009 IEEE International Symposium on Parallel and Distributed Processing with Applications, ISPA 2009. p. 203-210 8 p. 5207934. (Proceedings - 2009 IEEE International Symposium on Parallel and Distributed Processing with Applications, ISPA 2009).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Performance analysis of fully-adaptable CRC accelerators on an FPGA

Akagic, A. & Amano, H., 2012 Dec 12, Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012. p. 575-578 4 p. 6339374. (Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Performance and cost analysis of time-multiplexed execution on the dynamically reconfigurable processor

Amano, H., Abe, S., Hasegawa, Y., Deguchi, K. & Suzuki, M., 2005 Dec 1, Proceedings - 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2005. p. 315-316 2 p. 1508569. (Proceedings - 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2005; vol. 2005).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Performance and power analysis of time-multiplexed execution on dynamically reconfigurable processor

Hasegawa, Y., Abe, S., Kurotaki, S., Tuan, V. M., Katsura, N., Nakamura, T., Nishimura, T. & Amano, H., 2006 Jan 1, 20th International Parallel and Distributed Processing Symposium, IPDPS 2006. IEEE Computer Society, 1639431. (20th International Parallel and Distributed Processing Symposium, IPDPS 2006; vol. 2006).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Performance Estimation for Exascale Reconfigurable Dataflow Platforms

Yasudo, R., Coutinho, J., Varbanescu, A., Luk, W., Amano, H. & Becker, T., 2018 Dec, Proceedings - 2018 International Conference on Field-Programmable Technology, FPT 2018. Institute of Electrical and Electronics Engineers Inc., p. 317-320 4 p. 8742283. (Proceedings - 2018 International Conference on Field-Programmable Technology, FPT 2018).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Performance evaluation of 3-dimensional MIN with cache consistency maintenance mechanism

Tanabe, Y., Midorikawa, T., Shiraishi, D., Shigeno, M., Hanawa, T. & Amano, H., 2003 Dec 1, Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA 2003. Arabnia, H. R., Mun, Y., Arabnia, H. R. & Mun, Y. (eds.). p. 1148-1154 7 p. (Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications; vol. 3).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Performance evaluation of an FPGA-based biochemical simulator ReCSiP

Osana, Y., Yoshimi, M., Iwaoka, Y., Kojima, T., Nishikawa, Y., Funahashi, A., Hiroi, N., Kitano, H., Amano, H., Shibata, Y. & Iwanaga, N., 2006 Dec 1, Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL. p. 845-850 6 p. 4101089. (Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Performance Evaluation of a Prototype of RHiNET-2: A Network-based Distributed Parallel Computing System

Otsuka, T., Watanabe, K., Tsuchiya, J. I., Harada, H., Yamamoto, J., Nishi, H., Kudoh, T. & Amano, H., 2003 Dec 1, 21st IASTED International Multi-Conference on Applied Informatics. p. 738-743 6 p. (IASTED International Multi-Conference on Applied Informatics; vol. 21).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Performance evaluation of instruction set architecture of MBP-light: A distributed memory controller for a large scale multiprocessor

Suzuki, N. & Amano, H., 2003 Dec 1, Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA 2003. Arabnia, H. R., Mun, Y., Arabnia, H. R. & Mun, Y. (eds.). p. 1155-1161 7 p. (Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications; vol. 3).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Performance evaluation of multiple lookup tables algorithms for generating CRC on an FPGA

Akagić, A. & Amano, H., 2011 Aug 23, Proceedings of 2011 1st International Symposium on Access Spaces, ISAS 2011. p. 164-169 6 p. 5960941. (Proceedings of 2011 1st International Symposium on Access Spaces, ISAS 2011).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Performance Evaluation of PEACH3: Field-Programmable Gate Array Switch for Tightly Coupled Accelerators

Kaneda, T., Sakai, R., Nishikawa, N., Hanawa, T., Tsuruta, C. & Amano, H., 2017 Jun 7, Proceedings of the 8th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, HEART 2017. Association for Computing Machinery, 9

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Performance evaluation of power-aware multi-tree ethernet for HPC interconnects

Koibuchi, M., Watanabe, T., Minamihata, A., Nakao, M., Hiroyasu, T., Matsutani, H. & Amano, H., 2011 Dec 1, Proceedings - 2011 2nd International Conference on Networking and Computing, ICNC 2011. p. 50-57 8 p. 6131793. (Proceedings - 2011 2nd International Conference on Networking and Computing, ICNC 2011).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Performance evaluation of RHiNET 2/NI: A network interface for distributed parallel computing systems

Watanabe, K., Otsuka, T., Tsuchiya, J. I., Amano, H., Harada, H., Yamamoto, J., Nishi, H. & Kudoh, T., 2003 Dec 1, Proceedings - CCGrid 2003: 3rd IEEE/ACM International Symposium on Cluster Computing and the Grid. p. 318-325 8 p. 1199383. (Proceedings - CCGrid 2003: 3rd IEEE/ACM International Symposium on Cluster Computing and the Grid).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Citations (Scopus)

Performance evaluation of routing algorithms in RHiNET-2 cluster

Koibuchi, M., Watanabe, K., Kono, K., Jouraku, A. & Amano, H., 2003 Jan 1, Proceedings - IEEE International Conference on Cluster Computing, CLUSTER 2003. Institute of Electrical and Electronics Engineers Inc., p. 395-402 8 p. 1253339. (Proceedings - IEEE International Conference on Cluster Computing, ICCC; vol. 2003-January).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Citations (Scopus)

Performance evaluation of WASMII: A data driven computer on a virtual hardware

Ling, X. P. & Amano, H., 1993 Jan 1, PARLE 1993 - Parallel Architectures and Languages Europe - 5th International PARLE Conference, Proceedings. Bode, A., Reeve, M. & Wolf, G. (eds.). Springer Verlag, p. 610-621 12 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 694 LNCS).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Performance evaluation on low-latency communication mechanism of DIMMnet-2

Kitamura, A., Miyabe, Y., Miyashiro, T., Tanabe, N., Nakajo, H. & Amano, H., 2007 Dec 1, Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2007. p. 57-62 6 p. (Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Systems).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Performance improvement methodology for ClearSpeed's CSX600

Nishikawa, Y., Koibuchi, M., Yoshimi, M., Miura, K. & Amano, H., 2007 Dec 1, 2007 International Conference on Parallel Processing, ICPP. 4343884. (Proceedings of the International Conference on Parallel Processing).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Performance Prediction for Large-Scale Heterogeneous Platforms

Yasudo, R., Varbanescu, A. L., Coutinho, J. G. F., Luk, W. & Amano, H., 2018 Sep 7, Proceedings - 26th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2018. Institute of Electrical and Electronics Engineers Inc., 1 p. 8457669

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Power centric application mapping for dynamically reconfigurable processor array with Dual Vdd and Dual Vth

Hironaka, K. & Amano, H., 2011 Dec 1, Proceedings - 2011 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2011. p. 404-409 6 p. 6128611. (Proceedings - 2011 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2011).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Power Optimization Considering the Chip Temperature of Low Power Reconfigurable Accelerator CMA-SOTB

Fujita, Y., Okuhara, H., Masuyama, K. & Amano, H., 2016 Mar 2, Proceedings - 2015 3rd International Symposium on Computing and Networking, CANDAR 2015. Institute of Electrical and Electronics Engineers Inc., p. 21-29 9 p. 7424265

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Power reduction techniques for dynamically reconfigurable processor arrays

Nishimura, T., Hirai, K., Saito, Y., Nakamura, T., Hasegawa, Y., Tsutsusmi, S., Tunbunheng, V. & Amano, H., 2008 Nov 3, Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL. p. 305-310 6 p. 4629949. (Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

17 Citations (Scopus)