• 2531 Citations
  • 23 h-Index
1983 …2020

Research output per year

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Practical implementation of a network-based Stochastic biochemical simulation system on an FPGA

Yoshimi, M., Nishikawa, Y., Osana, Y., Funahashi, A., Hiroi, N., Shibata, Y., Yamada, H., Kitano, H. & Amano, H., 2008 Nov 3, Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL. p. 663-666 4 p. 4630034. (Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Prediction router: Yet another low latency on-chip router architecture

Matsutani, H., Koibuchi, M., Amano, H. & Yoshinaga, T., 2009 Apr 24, Proceedings - 15th International Symposium on High-Performance Computer Architecture, HPCA - 15 2009. p. 367-378 12 p. 4798274. (Proceedings - International Symposium on High-Performance Computer Architecture).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

60 Citations (Scopus)

Preliminary evaluation of batch-learning self-organizing map algorithm on a graphic processor

Shitara, A., Nishikawa, Y., Yoshimi, M., Abe, T., Ikemura, T. & Amano, H., 2010 Jul 20, Proceedings of the 9th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2010. p. 96-104 9 p. (Proceedings of the 9th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2010).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Preliminary evaluations of a FPGA-based-prototype of DIMMnet-2 network interface

Tanabe, N., Kitamura, A., Miyashiro, T., Miyabe, Y., Izawa, T., Hamada, Y., Nakajo, H. & Amano, H., 2005 Dec 1, IWIA 2005: Innovative Architecture for Future Generation High-Performance Processors and Systems. p. 119-127 9 p. 1587833. (Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems; vol. 2005).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Citations (Scopus)

Proposal of auto MPI expansion tool for cell broadband engine cluster

Nakahama, T., Yamada, M., Yoshimi, M. & Amano, H., 2011 Dec 1, Proceedings - 2011 2nd International Conference on Networking and Computing, ICNC 2011. p. 166-172 7 p. 6131802. (Proceedings - 2011 2nd International Conference on Networking and Computing, ICNC 2011).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Prototyping on using a DIMM slot as a high-performance I/O interface

Tanabe, N., Hamada, Y., Mitsuhashi, A., Nakajo, H., Yamamoto, J., Imashiro, H., Kudoh, T. & Amano, H., 2003 Jan 1, Innovative Architecture for Future Generation High-Performance Processors and Systems, IWIA 2003. Veidenbaum, A. & Joe, K. (eds.). IEEE Computer Society, p. 108-116 9 p. 1262788. (Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems; vol. 2003-January).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Randomizing Packet Memory Networks for Low-Latency Processor-Memory Communication

Fujiki, D., Matsutani, H., Koibuchi, M. & Amano, H., 2016 Mar 31, Proceedings - 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2016. Institute of Electrical and Electronics Engineers Inc., p. 168-175 8 p. 7445327

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Real chip evaluation of a low power CGRA with optimized application mapping

Kojima, T., Ando, N., Matshushita, Y., Okuhara, H., Doan, N. A. V. & Amano, H., 2018 Jun 20, Proceedings of the 9th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, HEART 2018. Association for Computing Machinery, a13

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Real chip performance evaluation on through chip interface IP for renesas SOTB 65nm process

Kayashima, H., Kojima, T., Okuhara, H., Shidei, T. & Amano, H., 2019 Nov, Proceedings - 2019 7th International Symposium on Computing and Networking Workshops, CANDARW 2019. Institute of Electrical and Electronics Engineers Inc., p. 269-274 6 p. 8951550. (Proceedings - 2019 7th International Symposium on Computing and Networking Workshops, CANDARW 2019).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Reconfigurable out-of-order mechanism generator for unstructured grid computation in computational fluid dynamics

Akamine, T., Inakagata, K., Osana, Y., Fujita, N. & Amano, H., 2012 Dec 12, Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012. p. 136-142 7 p. 6339277. (Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Reconfigurable systems: New activities in asia

Amano, H., Shibata, Y. & Uno, M., 2000, Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Springer Verlag, Vol. 1896. p. 585-594 10 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 1896).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Recursive diagonal torus: An interconnection network for massively parallel computers

Yang, Y. L., Amano, H., Shibamura, H. & Sueyoshi, T., 1993 Dec 1, Proceedings of the 5th IEEE Symposium on Parallel and Distributed Processing. Anon (ed.). Publ by IEEE, p. 591-594 4 p. (Proceedings of the 5th IEEE Symposium on Parallel and Distributed Processing).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

11 Citations (Scopus)

Reducing instruction TLB's leakage power consumption for embedded processors

Lei, Z., Xu, H., Ikebuchi, D., Amano, H., Sunata, T. & Namiki, M., 2010 Nov 24, 2010 International Conference on Green Computing, Green Comp 2010. p. 477-484 8 p. 5598277. (2010 International Conference on Green Computing, Green Comp 2010).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Reducing power consumption for dynamically reconfigurable processor array with partially fixed configuration mapping

Hironaka, K., Kimura, M., Saito, Y., Sano, T., Kato, M., Tunbunheng, V., Yasuda, Y. & Amano, H., 2010 Dec 1, Proceedings - 2010 International Conference on Field-Programmable Technology, FPT'10. p. 349-352 4 p. 5681431. (Proceedings - 2010 International Conference on Field-Programmable Technology, FPT'10).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Reducing power for dynamically reconfigurable processor array by reducing number of reconfigurations

Kimura, M., Hironaka, K. & Amano, H., 2011 Dec 1, 2011 International Conference on Field-Programmable Technology, FPT 2011. 6132707. (2011 International Conference on Field-Programmable Technology, FPT 2011).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Reduction calculator in an FPGA based switching Hub for high performance clusters

Kuhara, T., Tsuruta, C., Hanawa, T. & Amano, H., 2015 Oct 7, 25th International Conference on Field Programmable Logic and Applications, FPL 2015. Institute of Electrical and Electronics Engineers Inc., 7293985

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Research of PE array connection network for cool mega-array

Uno, R., Ozaki, N. & Amano, H., 2013 Aug 19, Proceedings - 27th International Conference on Advanced Information Networking and Applications Workshops, WAINA 2013. p. 144-149 6 p. 6550387. (Proceedings - 27th International Conference on Advanced Information Networking and Applications Workshops, WAINA 2013).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

RHiNET/NI: A reconfigurable network interface for cluster computing

Izu, N., Yokoyama, T., Tsuchiya, J., Watanabe, K. & Amano, H., 2002 Dec 1, Field-Programmable Logic and Applications: Reconfigurable Computing is Going Mainstream - 12th International Conference, FPL 2002, Proceedings. p. 1118-1121 4 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 2438 LNCS).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

RHiNET-3/SW: An 80-Gbit/s high-speed network switch for distributed parallel computing

Nishimura, S., Kudoh, T., Nishi, H., Yamamoto, J., Ueno, R., Harasawa, K., Fukuda, S., Shikichi, Y., Akutsu, S., Tasho, K. & Amano, H., 2001 Jan 1, HOT Interconnects 9, HIS 2001. Institute of Electrical and Electronics Engineers Inc., p. 119-123 5 p. 946703. (Proceedings - Symposium on the High Performance Interconnects, Hot Interconnects; vol. 2001-January).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

RHiNET A network for high performance parallel computing using locally distributed computers

Kudoh, T., Nishimura, S., Yamamoto, J., Nishi, H., Tatebe, O. & Amano, H., 1999 Jan 1, Innovative Architecture for Future Generation High-Performance Processors and Systems - 1999 International Workshop on Innovative Architectures, IWIA 1999. Nakashima, H. & Veidenbaum, A. (eds.). IEEE Computer Society, p. 69-73 5 p. 898844. (Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems; vol. 1999-November).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

18 Citations (Scopus)

RoMultiC: Fast and simple configuration data multicasting scheme for coarse grain reconfigurable devices

Tunbunheng, V., Suzuki, M. & Amano, H., 2005 Dec 1, Proceedings - 2005 IEEE International Conference on Field Programmable Technology. p. 129-136 8 p. 1568536. (Proceedings - 2005 IEEE International Conference on Field Programmable Technology; vol. 2005).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

38 Citations (Scopus)

Routing algorithms based on 2D turn model for irregular networks

Jouraku, A., Koibuchi, M., Amano, H. & Funahashi, A., 2002 Jan 1, Proceedings - International Symposium on Parallel Architectures, Algorithms and Networks, I-SPAN 2002. Hsu, D. F., Saldana, R. P. & Ibarra, O. H. (eds.). IEEE Computer Society, p. 289-294 6 p. 1004296. (Proceedings of the International Symposium on Parallel Architectures, Algorithms and Networks, I-SPAN; vol. 2002-January).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

13 Citations (Scopus)

RSM (RECEIVER SELECTABLE MULTICAST): A COMMUNICATION MECHANISM FOR MULTIPROCESSORS.

Amano, H., 1987 Jan 1, Unknown Host Publication Title. IEEE, p. 149-156 8 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Run-time power gating of on-chip routers using look-ahead routing

Matsutani, H., Koibuchi, M., Amano, H. & Wang, D., 2008 Aug 21, 2008 Asia and South Pacific Design Automation Conference, ASP-DAC. p. 55-60 6 p. 4484015. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

67 Citations (Scopus)

Scalable deep neural network accelerator cores with cubic integration using through chip interface

Sakamoto, R., Takata, R., Ishii, J., Kondo, M., Nakamura, H., Ohkubo, T., Kojima, T. & Amano, H., 2018 May 29, Proceedings - International SoC Design Conference 2017, ISOCC 2017. Institute of Electrical and Electronics Engineers Inc., p. 155-156 2 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Shared vs. Snoop: Evaluation of cache structure for single-chip multiprocessors

Kisuki, T., Wakabayashi, M., Yamamoto, J., Inoue, K. & Amano, H., 1997 Dec 1, Euro-Par 1997 Parallel Processing - Third International Conference, Proceedings. p. 793-797 5 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 1300 LNCS).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Significant papers from the first 25 years of the FPL conference

Leong, P. H. W., Amano, H., Anderson, J., Bertels, K., Cardoso, J. M. P., Diessel, O., Gogniat, G., Hutton, M., Lee, J., Luk, W., Lysaght, P., Platzner, M., Prasanna, V. K., Rissa, T., Silvano, C., So, H. & Wang, Y., 2015 Oct 7, 25th International Conference on Field Programmable Logic and Applications, FPL 2015. Institute of Electrical and Electronics Engineers Inc., 7293747

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

SLD-1(Silent Large Datapath): A ultra low power reconfigurable accelerator

Ozaki, N., Usami, K., Amano, H., Namiki, M., Nakamura, H. & Kondo, M., 2011 Jul 18, IEEE Symposium on Low-Power and High-Speed Chips - 2011 IEEE COOL Chips XIV, Proceedings. 5890918. (IEEE Symposium on Low-Power and High-Speed Chips - 2011 IEEE COOL Chips XIV, Proceedings).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

SNAIL: A multiprocessor based on the simple serial synchronized multistage interconnection network architecture

Sasahara, M., Terada, J., Zhou, L., Gaye, K., Yamato, J. I., Ogura, S. & Amano, H., 1994 Jan 1, Proceedings of the 1994 International Conference on Parallel Processing, ICPP 1994. Institute of Electrical and Electronics Engineers Inc., p. I117-I120 4115704. (Proceedings of the International Conference on Parallel Processing; vol. 1).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Software environment for WASMII: A data driven machine with a virtual hardware

Chen, X. Y., Ling, X. P. & Amano, H., 1994 Jan 1, Field-Programmable Logic: Architectures, Synthesis and Applications - 4th International Workshop on Field-Programmable Logic and Applications, FPL 1994, Proceedings. Hartenstein, R. W. & Servit, M. Z. (eds.). Springer Verlag, p. 208-219 12 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 849 LNCS).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Sparse 3-D NoCs with inductive coupling

Koibuchi, M., Leong, L., Totoki, T., Niwa, N., Matsutani, H., Amano, H. & Casanova, H., 2019 Jun 2, Proceedings of the 56th Annual Design Automation Conference 2019, DAC 2019. Institute of Electrical and Electronics Engineers Inc., a49. (Proceedings - Design Automation Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Spatial and temporal granularity limits of body biasing in UTBB-FDSOI

Kuhn, J. M., Peterson, D., Amano, H., Bringmann, O. & Rosenstiel, W., 2015 Apr 22, Proceedings -Design, Automation and Test in Europe, DATE. Institute of Electrical and Electronics Engineers Inc., Vol. 2015-April. p. 876-879 4 p. 7092508

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Stabilizing Path Modification of Power-Aware On/Off Interconnection Networks

Montañana, J. M., Koibuchi, M., Matsutani, H. & Amano, H., 2010 Oct 28, Proceedings - 2010 IEEE International Conference on Networking, Architecture and Storage, NAS 2010. p. 218-227 10 p. 5575649. (Proceedings - 2010 IEEE International Conference on Networking, Architecture and Storage, NAS 2010).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Stream applications on the dynamically reconfigurable processor

Suzuki, M., Hasegawa, Y., Yamada, Y., Kaneko, N., Deguchi, K., Amano, H., Anjo, K., Motomura, M., Wakabayashi, K., Toi, T. & Awashima, T., 2004 Dec 1, Proceedings - 2004 IEEE International Conference on Field-Programmable Technology, FPT '04. Diessel, O. & Williams, J. (eds.). p. 137-144 8 p. (Proceedings - 2004 IEEE International Conference on Field-Programmable Technology, FPT '04).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

30 Citations (Scopus)

Superpixel accelerator for computer vision applications on arria 10 SoC

Akagic, A., Buza, E., Turcinhodzic, R., Haseljic, H., Hiroyuki, N. & Amano, H., 2018 Jul 11, Proceedings - 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2018. Institute of Electrical and Electronics Engineers Inc., p. 55-60 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Switching region analysis for SOTB technology

Cortes, C. & Amano, H., 2017 Jun 27, 2017 International Caribbean Conference on Devices, Circuits and Systems, ICCDCS 2017. Institute of Electrical and Electronics Engineers Inc., p. 33-36 4 p. 7959717

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Task level pipelining with PEACH2: An FPGA switching fabric for high performance computing

Miyajima, T., Kuhara, T., Hanawa, T., Amano, H. & Boku, T., 2013 Dec 1, FPT 2013 - Proceedings of the 2013 International Conference on Field Programmable Technology. p. 466-469 4 p. 6718416. (FPT 2013 - Proceedings of the 2013 International Conference on Field Programmable Technology).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

The design and implementation of scalable deep neural network accelerator cores

Sakamoto, R., Takata, R., Ishii, J., Kondo, M., Nakamura, H., Ohkubo, T., Kojima, T. & Amano, H., 2018 Mar 26, Proceedings - IEEE 11th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2017. Institute of Electrical and Electronics Engineers Inc., Vol. 2018-January. p. 13-20 8 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

The design of scalable stochastic biochemical simulator on FPGA

Yoshimi, M., Osana, Y., Iwaoka, Y., Funahashi, A., Hiroi, N., Shibata, Y., Iwanaga, N., Kitano, H. & Amano, H., 2005 Dec 1, Proceedings - 2005 IEEE International Conference on Field Programmable Technology. p. 339-340 2 p. 1568590. (Proceedings - 2005 IEEE International Conference on Field Programmable Technology; vol. 2005).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

The evaluation of dynamic load balancing algorithm on RHiNET-2

Kitamura, A., Watanabe, K., Otsuka, T. & Amano, H., 2003 Dec 1, Proceedings of the Fifteenth IASTED International Conference on Parallel and Distributed Computing and Sytems. Gonzalez, T. (ed.). 1 ed. p. 262-267 6 p. (Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Systems; vol. 15, no. 1).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

The evaluation of partial reconfiguration for a multi-board FPGA system FiCSW

Yamakura, M., Hironaka, K., Azegami, K., Musha, K. & Amano, H., 2019 Jun 6, Proceedings of the 10th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, HEART 2019. Association for Computing Machinery, 15. (ACM International Conference Proceeding Series).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

The preliminary evaluation of MBP-light with two protocol policies for a massively parallel processor-JUMP-1

Hiroaki, I., Anjo, K., Yamamoto, J., Tanabe, J., Wakabayashi, M., Sato, M., Amano, H. & Hiraki, K., 1999 Jan 1, Proceedings - Frontiers 1999, 7th Symposium on the Frontiers of Massively Parallel Computation. Institute of Electrical and Electronics Engineers Inc., p. 268-275 8 p. 750609. (Proceedings - Frontiers 1999, 7th Symposium on the Frontiers of Massively Parallel Computation).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

The realtime image processing demonstration with CMA-1: An ultra low-power reconfigurable accelerator

Hironaka, K., Ozaki, N. & Amano, H., 2011 Dec 1, 2011 International Conference on Field-Programmable Technology, FPT 2011. 6132686. (2011 International Conference on Field-Programmable Technology, FPT 2011).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Three-dimensional layout of on-chip tree-based networks

Matsutani, H., Koibuchi, M., Hsu, D. F. & Amano, H., 2008 Aug 15, Proceedings - 9th International Symposium on Parallel Architectures, Algorithms and Networks, I-SPAN 2008. p. 281-288 8 p. 4520228. (Proceedings of the International Symposium on Parallel Architectures, Algorithms and Networks, I-SPAN).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Citations (Scopus)

Tightly-coupled multi-layer topologies for 3-D NoCs

Matsutani, H., Koibuchi, M. & Amano, H., 2007 Dec 1, 2007 International Conference on Parallel Processing, ICPP. 4343882. (Proceedings of the International Conference on Parallel Processing).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

62 Citations (Scopus)

Time and space-multiplexed compilation challenges for dynamically reconfigurable processors

Toi, T., Awashima, T., Motomura, M. & Amano, H., 2011 Oct 13, 54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011. 6026300. (Midwest Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Towards an optimized multi FPGA architecture with STDM network: A preliminary study

Hironaka, K., Doan, N. A. V. & Amano, H., 2018 Jan 1, Applied Reconfigurable Computing: Architectures, Tools, and Applications - 14th International Symposium, ARC 2018, Proceedings. Springer Verlag, p. 142-150 9 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 10824 LNCS).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Towards tightly-coupled datacenter with free-space optical links

Hu, Y., Matsutani, H., Hara, H., Amano, H., Fujiwara, I. & Koibuchi, M., 2017 Sep 17, 2017 International Conference on Cloud and Big Data Computing, ICCBDC 2017. Association for Computing Machinery, p. 33-39 7 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Towards unification of accelerated computing and interconnection for extreme-scale computing

Hanawa, T., Kodama, Y., Boku, T., Amano, H., Murai, H., Umemura, M. & Sato, M., 2015 Jan 1, Applied Reconfigurable Computing - 11th International Symposium, ARC 2015, Proceedings. Diniz, P. C., Sano, K., Hübner, M. & Soudris, D. (eds.). Springer Verlag, p. 463-474 12 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 9040).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Trade-off analysis of fine-grained power gating methods for functional units in a CPU

Wang, W., Ohta, Y., Ishii, Y., Usami, K. & Amano, H., 2012 Jul 25, Symposium on Low-Power and High-Speed Chips - Proceedings for 2012 IEEE COOL Chips XV. 6216587. (Symposium on Low-Power and High-Speed Chips - Proceedings for 2012 IEEE COOL Chips XV).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)