• Source: Scopus
  • Calculated based on no. of publications stored in Pure and citations from Scopus
1983 …2022

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  • Refinements in Data Manipulation Method for Coarse Grained Reconfigurable Architectures

    Kojima, T. & Amano, H., 2019 Jul, Proceedings - 2019 14th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip, ReCoSoC 2019. Fornaciari, W., Novo, D. & Indrusiak, L. S. (eds.). Institute of Electrical and Electronics Engineers Inc., p. 113-120 8 p. 9034924. (Proceedings - 2019 14th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip, ReCoSoC 2019).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • Reduction calculator in an FPGA based switching Hub for high performance clusters

    Kuhara, T., Tsuruta, C., Hanawa, T. & Amano, H., 2015 Oct 7, 25th International Conference on Field Programmable Logic and Applications, FPL 2015. Institute of Electrical and Electronics Engineers Inc., 7293985

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    10 Citations (Scopus)
  • Reducing power for dynamically reconfigurable processor array by reducing number of reconfigurations

    Kimura, M., Hironaka, K. & Amano, H., 2011 Dec 1, 2011 International Conference on Field-Programmable Technology, FPT 2011. 6132707. (2011 International Conference on Field-Programmable Technology, FPT 2011).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • Reducing power consumption for dynamically reconfigurable processor array with partially fixed configuration mapping

    Hironaka, K., Kimura, M., Saito, Y., Sano, T., Kato, M., Tunbunheng, V., Yasuda, Y. & Amano, H., 2010 Dec 1, Proceedings - 2010 International Conference on Field-Programmable Technology, FPT'10. p. 349-352 4 p. 5681431. (Proceedings - 2010 International Conference on Field-Programmable Technology, FPT'10).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    1 Citation (Scopus)
  • Reducing instruction TLB's leakage power consumption for embedded processors

    Lei, Z., Xu, H., Ikebuchi, D., Amano, H., Sunata, T. & Namiki, M., 2010, 2010 International Conference on Green Computing, Green Comp 2010. IEEE Computer Society, p. 477-484 8 p. 5598277. (2010 International Conference on Green Computing, Green Comp 2010).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    2 Citations (Scopus)
  • Recursive diagonal torus: An interconnection network for massively parallel computers

    Yang, Y. L., Amano, H., Shibamura, H. & Sueyoshi, T., 1993 Dec 1, Proceedings of the 5th IEEE Symposium on Parallel and Distributed Processing. Anon (ed.). Publ by IEEE, p. 591-594 4 p. (Proceedings of the 5th IEEE Symposium on Parallel and Distributed Processing).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    12 Citations (Scopus)
  • Reconfigurable systems: New activities in asia

    Amano, H., Shibata, Y. & Uno, M., 2000, Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing - 10th International Conference, FPL 2000, Proceedings. Hartenstein, R. W. & Grunbacher, H. (eds.). Springer Verlag, p. 585-594 10 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 1896).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    5 Citations (Scopus)
  • Reconfigurable out-of-order mechanism generator for unstructured grid computation in computational fluid dynamics

    Akamine, T., Inakagata, K., Osana, Y., Fujita, N. & Amano, H., 2012 Dec 12, Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012. p. 136-142 7 p. 6339277. (Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    5 Citations (Scopus)
  • Real chip performance evaluation on through chip interface IP for renesas SOTB 65nm process

    Kayashima, H., Kojima, T., Okuhara, H., Shidei, T. & Amano, H., 2019 Nov, Proceedings - 2019 7th International Symposium on Computing and Networking Workshops, CANDARW 2019. Institute of Electrical and Electronics Engineers Inc., p. 269-274 6 p. 8951550. (Proceedings - 2019 7th International Symposium on Computing and Networking Workshops, CANDARW 2019).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • Real chip evaluation of a low power CGRA with optimized application mapping

    Kojima, T., Ando, N., Matshushita, Y., Okuhara, H., Doan, N. A. V. & Amano, H., 2018 Jun 20, Proceedings of the 9th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, HEART 2018. Association for Computing Machinery, a13. (ACM International Conference Proceeding Series).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    5 Citations (Scopus)
  • Randomizing Packet Memory Networks for Low-Latency Processor-Memory Communication

    Fujiki, D., Matsutani, H., Koibuchi, M. & Amano, H., 2016 Mar 31, Proceedings - 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2016. Cotronis, Y., Daneshtalab, M. & Papadopoulos, G. A. (eds.). Institute of Electrical and Electronics Engineers Inc., p. 168-175 8 p. 7445327. (Proceedings - 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2016).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    4 Citations (Scopus)
  • Prototyping on using a DIMM slot as a high-performance I/O interface

    Tanabe, N., Hamada, Y., Mitsuhashi, A., Nakajo, H., Yamamoto, J., Imashiro, H., Kudoh, T. & Amano, H., 2003, Innovative Architecture for Future Generation High-Performance Processors and Systems, IWIA 2003. Veidenbaum, A. & Joe, K. (eds.). IEEE Computer Society, p. 108-116 9 p. 1262788. (Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems; vol. 2003-January).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    3 Citations (Scopus)
  • Proposal of auto MPI expansion tool for cell broadband engine cluster

    Nakahama, T., Yamada, M., Yoshimi, M. & Amano, H., 2011, Proceedings - 2011 2nd International Conference on Networking and Computing, ICNC 2011. p. 166-172 7 p. 6131802. (Proceedings - 2011 2nd International Conference on Networking and Computing, ICNC 2011).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • Preliminary evaluations of a FPGA-based-prototype of DIMMnet-2 network interface

    Tanabe, N., Kitamura, A., Miyashiro, T., Miyabe, Y., Izawa, T., Hamada, Y., Nakajo, H. & Amano, H., 2005, IWIA 2005: Innovative Architecture for Future Generation High-Performance Processors and Systems. IEEE Computer Society, p. 9-17 9 p. 1587833. (Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems; vol. 2005).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    8 Citations (Scopus)
  • Preliminary evaluation of batch-learning self-organizing map algorithm on a graphic processor

    Shitara, A., Nishikawa, Y., Yoshimi, M., Abe, T., Ikemura, T. & Amano, H., 2010, Proceedings of the 9th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2010. Acta Press, p. 96-104 9 p. (Proceedings of the 9th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2010).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • Prediction router: Yet another low latency on-chip router architecture

    Matsutani, H., Koibuchi, M., Amano, H. & Yoshinaga, T., 2009, Proceedings - 15th International Symposium on High-Performance Computer Architecture, HPCA - 15 2009. IEEE Computer Society, p. 367-378 12 p. 4798274. (Proceedings - International Symposium on High-Performance Computer Architecture).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    65 Citations (Scopus)
  • Practical implementation of a network-based Stochastic biochemical simulation system on an FPGA

    Yoshimi, M., Nishikawa, Y., Osana, Y., Funahashi, A., Hiroi, N., Shibata, Y., Yamada, H., Kitano, H. & Amano, H., 2008 Nov 3, Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL. p. 663-666 4 p. 4630034. (Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    5 Citations (Scopus)
  • Power reduction techniques for dynamically reconfigurable processor arrays

    Nishimura, T., Hirai, K., Saito, Y., Nakamura, T., Hasegawa, Y., Tsutsusmi, S., Tunbunheng, V. & Amano, H., 2008 Nov 3, Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL. p. 305-310 6 p. 4629949. (Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    18 Citations (Scopus)
  • Power Optimization Considering the Chip Temperature of Low Power Reconfigurable Accelerator CMA-SOTB

    Fujita, Y., Okuhara, H., Masuyama, K. & Amano, H., 2016 Mar 2, Proceedings - 2015 3rd International Symposium on Computing and Networking, CANDAR 2015. Institute of Electrical and Electronics Engineers Inc., p. 21-29 9 p. 7424265

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    3 Citations (Scopus)
  • Power centric application mapping for dynamically reconfigurable processor array with Dual Vdd and Dual Vth

    Hironaka, K. & Amano, H., 2011 Dec 1, Proceedings - 2011 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2011. p. 404-409 6 p. 6128611. (Proceedings - 2011 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2011).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    2 Citations (Scopus)
  • Performance Prediction for Large-Scale Heterogeneous Platforms

    Yasudo, R., Varbanescu, A. L., Coutinho, J. G. F., Luk, W. & Amano, H., 2018 Sep 7, Proceedings - 26th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2018. Institute of Electrical and Electronics Engineers Inc., p. 220 1 p. 8457669. (Proceedings - 26th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2018).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • Performance improvement methodology for ClearSpeed's CSX600

    Nishikawa, Y., Koibuchi, M., Yoshimi, M., Miura, K. & Amano, H., 2007 Dec 1, 2007 International Conference on Parallel Processing, ICPP. 4343884. (Proceedings of the International Conference on Parallel Processing).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    6 Citations (Scopus)
  • Performance evaluation on low-latency communication mechanism of DIMMnet-2

    Kitamura, A., Miyabe, Y., Miyashiro, T., Tanabe, N., Nakajo, H. & Amano, H., 2007 Dec 1, Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2007. p. 57-62 6 p. (Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Systems).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    4 Citations (Scopus)
  • Performance evaluation of WASMII: A data driven computer on a virtual hardware

    Ling, X. P. & Amano, H., 1993 Jan 1, PARLE 1993 - Parallel Architectures and Languages Europe - 5th International PARLE Conference, Proceedings. Bode, A., Reeve, M. & Wolf, G. (eds.). Springer Verlag, p. 610-621 12 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 694 LNCS).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    4 Citations (Scopus)
  • Performance evaluation of routing algorithms in RHiNET-2 cluster

    Koibuchi, M., Watanabe, K., Kono, K., Jouraku, A. & Amano, H., 2003 Jan 1, Proceedings - IEEE International Conference on Cluster Computing, CLUSTER 2003. Institute of Electrical and Electronics Engineers Inc., p. 395-402 8 p. 1253339. (Proceedings - IEEE International Conference on Cluster Computing, ICCC; vol. 2003-January).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    15 Citations (Scopus)
  • Performance evaluation of RHiNET 2/NI: A network interface for distributed parallel computing systems

    Watanabe, K., Otsuka, T., Tsuchiya, J. I., Amano, H., Harada, H., Yamamoto, J., Nishi, H. & Kudoh, T., 2003 Dec 1, Proceedings - CCGrid 2003: 3rd IEEE/ACM International Symposium on Cluster Computing and the Grid. p. 318-325 8 p. 1199383. (Proceedings - CCGrid 2003: 3rd IEEE/ACM International Symposium on Cluster Computing and the Grid).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    10 Citations (Scopus)
  • Performance evaluation of power-aware multi-tree ethernet for HPC interconnects

    Koibuchi, M., Watanabe, T., Minamihata, A., Nakao, M., Hiroyasu, T., Matsutani, H. & Amano, H., 2011, Proceedings - 2011 2nd International Conference on Networking and Computing, ICNC 2011. p. 50-57 8 p. 6131793. (Proceedings - 2011 2nd International Conference on Networking and Computing, ICNC 2011).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    1 Citation (Scopus)
  • Performance Evaluation of PEACH3: Field-Programmable Gate Array Switch for Tightly Coupled Accelerators

    Kaneda, T., Sakai, R., Nishikawa, N., Hanawa, T., Tsuruta, C. & Amano, H., 2017 Jun 7, Proceedings of the 8th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, HEART 2017. Association for Computing Machinery, 9. (ACM International Conference Proceeding Series).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • Performance evaluation of multiple lookup tables algorithms for generating CRC on an FPGA

    Akagić, A. & Amano, H., 2011 Aug 23, Proceedings of 2011 1st International Symposium on Access Spaces, ISAS 2011. p. 164-169 6 p. 5960941. (Proceedings of 2011 1st International Symposium on Access Spaces, ISAS 2011).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    5 Citations (Scopus)
  • Performance evaluation of instruction set architecture of MBP-light: A distributed memory controller for a large scale multiprocessor

    Suzuki, N. & Amano, H., 2003 Dec 1, Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA 2003. Arabnia, H. R., Mun, Y., Arabnia, H. R. & Mun, Y. (eds.). p. 1155-1161 7 p. (Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications; vol. 3).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • Performance Evaluation of a Prototype of RHiNET-2: A Network-based Distributed Parallel Computing System

    Otsuka, T., Watanabe, K., Tsuchiya, J. I., Harada, H., Yamamoto, J., Nishi, H., Kudoh, T. & Amano, H., 2003 Dec 1, 21st IASTED International Multi-Conference on Applied Informatics. p. 738-743 6 p. (IASTED International Multi-Conference on Applied Informatics; vol. 21).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    7 Citations (Scopus)
  • Performance evaluation of an FPGA-based biochemical simulator ReCSiP

    Osana, Y., Yoshimi, M., Iwaoka, Y., Kojima, T., Nishikawa, Y., Funahashi, A., Hiroi, N., Kitano, H., Amano, H., Shibata, Y. & Iwanaga, N., 2006 Dec 1, Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL. p. 845-850 6 p. 4101089. (Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    4 Citations (Scopus)
  • Performance evaluation of 3-dimensional MIN with cache consistency maintenance mechanism

    Tanabe, Y., Midorikawa, T., Shiraishi, D., Shigeno, M., Hanawa, T. & Amano, H., 2003, Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA 2003. Arabnia, H. R., Mun, Y., Arabnia, H. R. & Mun, Y. (eds.). p. 1148-1154 7 p. (Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications; vol. 3).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    1 Citation (Scopus)
  • Performance Estimation for Exascale Reconfigurable Dataflow Platforms

    Yasudo, R., Coutinho, J., Varbanescu, A., Luk, W., Amano, H. & Becker, T., 2018 Dec, Proceedings - 2018 International Conference on Field-Programmable Technology, FPT 2018. Institute of Electrical and Electronics Engineers Inc., p. 317-320 4 p. 8742283. (Proceedings - 2018 International Conference on Field-Programmable Technology, FPT 2018).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    4 Citations (Scopus)
  • Performance and power analysis of time-multiplexed execution on dynamically reconfigurable processor

    Hasegawa, Y., Abe, S., Kurotaki, S., Tuan, V. M., Katsura, N., Nakamura, T., Nishimura, T. & Amano, H., 2006, 20th International Parallel and Distributed Processing Symposium, IPDPS 2006. IEEE Computer Society, 1639431. (20th International Parallel and Distributed Processing Symposium, IPDPS 2006; vol. 2006).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    2 Citations (Scopus)
  • Performance and cost analysis of time-multiplexed execution on the dynamically reconfigurable processor

    Amano, H., Abe, S., Hasegawa, Y., Deguchi, K. & Suzuki, M., 2005 Dec 1, Proceedings - 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2005. p. 315-316 2 p. 1508569. (Proceedings - 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2005; vol. 2005).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    8 Citations (Scopus)
  • Performance analysis of fully-adaptable CRC accelerators on an FPGA

    Akagic, A. & Amano, H., 2012 Dec 12, Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012. p. 575-578 4 p. 6339374. (Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • Performance analysis of clearspeed's CSX600 interconnects

    Nishikawa, Y., Koibuchi, M., Yoshimi, M., Shitara, A., Miura, K. & Amano, H., 2009 Nov 19, Proceedings - 2009 IEEE International Symposium on Parallel and Distributed Processing with Applications, ISPA 2009. p. 203-210 8 p. 5207934. (Proceedings - 2009 IEEE International Symposium on Parallel and Distributed Processing with Applications, ISPA 2009).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    1 Citation (Scopus)
  • Performance analysis for the arbitor of IEEE standard backplane bus Futurebus/Futurebus+

    Yamamoto, O., Takemoto, T., Kimura, T. & Amano, H., 1993 Jan 1, Proc IEEE 1993 Pac Rim Conf Commun Comput Signal Process. Publ by IEEE, p. 386-389 4 p. (Proc IEEE 1993 Pac Rim Conf Commun Comput Signal Process).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    1 Citation (Scopus)
  • Performance/cost trade-off evaluation for the DCT implementation on the dynamically reconfigurable processor

    Tuan, V. M., Hasegawa, Y., Katsura, N. & Amano, H., 2006 Jan 1, Reconfigurable Computing: Architectures and Applications - Second International Workshop, ARC 2006, Revised Selected Papers. Springer Verlag, p. 115-121 7 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 3985 LNCS).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    1 Citation (Scopus)
  • Performance, cost, and power evaluations of on-chip network topologies in FPGAs

    In, S., Matsutani, H., Koibuchi, M., Wang, D. & Amano, H., 2010 Jul 20, Proceedings of the 9th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2010. p. 181-189 9 p. (Proceedings of the 9th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2010).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • Performance, cost, and energy evaluation of fat H-tree: A cost-efficient tree-based on-chip network

    Matsutani, H., Koibuchi, M. & Amano, H., 2007 Sep 24, Proceedings - 21st International Parallel and Distributed Processing Symposium, IPDPS 2007; Abstracts and CD-ROM. 4227999. (Proceedings - 21st International Parallel and Distributed Processing Symposium, IPDPS 2007; Abstracts and CD-ROM).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    22 Citations (Scopus)
  • Partially reconfigurable flux calculation scheme in advection term computation

    Talip, M. S. A., Akamine, T., Hatto, M., Osana, Y., Fujita, N. & Amano, H., 2013 Dec 1, FPT 2013 - Proceedings of the 2013 International Conference on Field Programmable Technology. p. 382-385 4 p. 6718393. (FPT 2013 - Proceedings of the 2013 International Conference on Field Programmable Technology).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    2 Citations (Scopus)
  • Overwrite configuration technique in multicast configuration scheme for dynamically reconfigurable processor arrays

    Tsutsumi, S., Tunbunheng, V., Hasegawa, Y., Parimala, A., Nakamura, T., Nishimura, T. & Amano, H., 2007, ICFPT 2007 - International Conference on Field Programmable Technology. p. 273-276 4 p. 4439264. (ICFPT 2007 - International Conference on Field Programmable Technology).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    4 Citations (Scopus)
  • Order/Radix Problem: Towards Low End-to-End Latency Interconnection Networks

    Yasudo, R., Koibuchi, M., Nakano, K., Matsutani, H. & Amano, H., 2017 Sep 1, Proceedings - 46th International Conference on Parallel Processing, ICPP 2017. Institute of Electrical and Electronics Engineers Inc., p. 322-331 10 p. 8025306. (Proceedings of the International Conference on Parallel Processing).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    3 Citations (Scopus)
  • Optimized core-links for low-latency NoCs

    Kawano, R., Tade, S., Fujiwara, I., Matsutani, H., Amano, H. & Koibuchi, M., 2015, Proceedings - 23rd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2015. Lilius, J., Daneshtalab, M., Brorsson, M., Leppanen, V. & Aldinucci, M. (eds.). Institute of Electrical and Electronics Engineers Inc., p. 172-176 5 p. 7092716. (Proceedings - 23rd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2015).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • On-the-fly data compression/decompression mechanism with ExpEther

    Shimura, H., Mitsuishi, T., Amano, H., Kan, M. & Yoshikawa, T., 2017 Jan 13, Proceedings - 2016 4th International Symposium on Computing and Networking, CANDAR 2016. Institute of Electrical and Electronics Engineers Inc., p. 112-118 7 p. 7818601. (Proceedings - 2016 4th International Symposium on Computing and Networking, CANDAR 2016).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    1 Citation (Scopus)
  • On-chip detection methodology for break-even time of power gated function units

    Usami, K., Goto, Y., Matsunaga, K., Koyama, S., Ikebuchi, D., Amano, H. & Nakamura, H., 2011 Sep 19, IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011. p. 241-246 6 p. 5993643. (Proceedings of the International Symposium on Low Power Electronics and Design).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    15 Citations (Scopus)
  • On-chip decentralized routers with balanced pipelines for avoiding interconnect bottleneck

    Yasudo, R., Matsutani, H., Koibuchi, M., Amano, H. & Nakamura, T., 2015 Sep 28, Proceedings - 2015 9th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2015. Marculescu, D., Ivanov, A., Pande, P. P. & Flich, J. (eds.). Association for Computing Machinery, Inc, 2817280. (Proceedings - 2015 9th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2015).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    1 Citation (Scopus)
  • Non-Volatile Coarse Grained Reconfigurable Array Enabling Two-step Store Control for Energy Minimization

    Usami, K., Akiba, S., Amano, H., Ikezoe, T., Hiraga, K., Suzuki, K. & Kanda, Y., 2020 Apr, IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2020 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 9097630. (IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2020 - Proceedings).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    1 Citation (Scopus)