• Source: Scopus
  • Calculated based on no. of publications stored in Pure and citations from Scopus
1983 …2022

Research activity per year

If you made any changes in Pure these will be visible here soon.
Filter
Conference contribution

Search results

  • Demonstration of flow-in-cloud: A multi-FPGA system

    Hironaka, K., Iizuka, K., Ben Ahmed, A., Imdad Ullah, M. M., Yamauchi, Y., Sun, Y., Yamakura, M., Hiruma, A. & Amano, H., 2019 Sep, Proceedings - 29th International Conference on Field-Programmable Logic and Applications, FPL 2019. Sourdis, I., Bouganis, C-S., Alvarez, C., Toledo Diaz, L. A., Valero, P. & Martorell, X. (eds.). Institute of Electrical and Electronics Engineers Inc., p. 417-418 2 p. 8892139. (Proceedings - 29th International Conference on Field-Programmable Logic and Applications, FPL 2019).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    2 Citations (Scopus)
  • Deep learning on high performance FPGA switching boards: Flow-in-cloud

    Musha, K., Kudoh, T. & Amano, H., 2018, Applied Reconfigurable Computing: Architectures, Tools, and Applications - 14th International Symposium, ARC 2018, Proceedings. Voros, N., Keramidas, G., Antonopoulos, C., Huebner, M., Diniz, P. C. & Goehringer, D. (eds.). Springer Verlag, p. 43-54 12 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 10824 LNCS).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    4 Citations (Scopus)
  • Deadlock-free layered routing for infiniband networks

    Kawano, R., Matsutani, H. & Amano, H., 2019 Nov, Proceedings - 2019 7th International Symposium on Computing and Networking Workshops, CANDARW 2019. Institute of Electrical and Electronics Engineers Inc., p. 84-90 7 p. 8951557. (Proceedings - 2019 7th International Symposium on Computing and Networking Workshops, CANDARW 2019).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • Dataflow partitioning and scheduling algorithms for WASMII, a virtual hardware

    Takayama, A., Shibata, Y., Iwai, K. & Amano, H., 2000, Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Springer Verlag, Vol. 1896. p. 685-694 10 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 1896).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    8 Citations (Scopus)
  • Cost effective implementation of flux limiter functions using partial reconfiguration

    Abu Talip, M. S., Akamine, T., Osana, Y., Fujita, N. & Amano, H., 2012, Reconfigurable Computing: Architectures, Tools and Applications - 8th International Symposium, ARC 2012, Proceedings. p. 215-226 12 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 7199 LNCS).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    1 Citation (Scopus)
  • Cool mega-array: A highly energy efficient reconfigurable accelerator

    Ozaki, N., Yoshihiro, Y., Saito, Y., Ikebuchi, D., Kimura, M., Amano, H., Nakamura, H., Usami, K., Namiki, M. & Kondo, M., 2011, 2011 International Conference on Field-Programmable Technology, FPT 2011. 6132668. (2011 International Conference on Field-Programmable Technology, FPT 2011).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    15 Citations (Scopus)
  • Configuring area and performance: Empirical evaluation on an FPGA-based biochemical simulator

    Ooya, T., Yamada, H., Ishimori, T., Shibata, Y., Osana, Y., Oguri, K., Yoshimi, M., Nishikawa, Y., Funahashi, A., Hiroi, N. & Amano, H., 2009 Nov 25, FPL 09: 19th International Conference on Field Programmable Logic and Applications. p. 679-682 4 p. 5272335. (FPL 09: 19th International Conference on Field Programmable Logic and Applications).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    2 Citations (Scopus)
  • CMA-Cube: A scalable reconfigurable accelerator with 3-D wireless inductive coupling interconnect

    Koizumi, Y., Sasaki, E., Amano, H., Matsutani, H., Take, Y., Kuroda, T., Sakamoto, R., Namiki, M., Usami, K., Kondo, M. & Nakamura, H., 2012 Dec 12, Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012. p. 543-546 4 p. 6339375. (Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    6 Citations (Scopus)
  • CMA-2: The second prototype of a low power reconfigurable accelerator

    Izawa, M., Ozaki, N., Yasuda, Y., Kimura, M. & Amano, H., 2012 Apr 26, ASP-DAC 2012 - 17th Asia and South Pacific Design Automation Conference. p. 471-472 2 p. 6164996. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    1 Citation (Scopus)
  • CLAHE implementation on a low-end FPGA board by high-level synthesis

    Honda, K., Wei, K., Arai, M. & Amano, H., 2020 Nov, Proceedings - 2020 8th International Symposium on Computing and Networking Workshops, CANDARW 2020. Institute of Electrical and Electronics Engineers Inc., p. 282-285 4 p. 9355944. (Proceedings - 2020 8th International Symposium on Computing and Networking Workshops, CANDARW 2020).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • Castle of chips: A new chip stacking structure with wireless inductive coupling for large scale 3-D multicore systems

    Amano, H., 2012 Dec 14, Proceedings of the 2012 15th International Conference on Network-Based Information Systems, NBIS 2012. p. 820-825 6 p. 6354931. (Proceedings of the 2012 15th International Conference on Network-Based Information Systems, NBIS 2012).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    4 Citations (Scopus)
  • Cache coherence protocol for home proxy cache on RHiNET and its preliminary performance estimation

    Nakajo, J., Ishii, M., Yamamoto, J., Kudo, T., Yokoyama, T., Tsuchiya, J. & Amano, H., 2000, Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems. IEEE Computer Society, Vol. 2001-January. p. 53-60 8 p. 955197

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    2 Citations (Scopus)
  • C4: An FPGA-based compression algorithm for expether

    Shimura, H., Noda, H. & Amano, H., 2018 Dec 26, Proceedings - 2018 6th International Symposium on Computing and Networking Workshops, CANDARW 2018. Institute of Electrical and Electronics Engineers Inc., p. 356-362 7 p. 8590926. (Proceedings - 2018 6th International Symposium on Computing and Networking Workshops, CANDARW 2018).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • Building block operating system for 3D stacked computer systems with inductive coupling interconnect

    Hamada, S., Koshiba, A., Namiki, M. & Amano, H., 2018 May 29, Proceedings - International SoC Design Conference 2017, ISOCC 2017. Institute of Electrical and Electronics Engineers Inc., p. 157-158 2 p. (Proceedings - International SoC Design Conference 2017, ISOCC 2017).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • Building block multi-chip systems using inductive coupling through chip interface

    Amano, H., Kuroda, T., Nakamura, H., Usami, K., Kondo, M., Matsutani, H. & Namiki, M., 2018 May 29, Proceedings - International SoC Design Conference 2017, ISOCC 2017. Institute of Electrical and Electronics Engineers Inc., p. 152-154 3 p. (Proceedings - International SoC Design Conference 2017, ISOCC 2017).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • Break even time analysis using empirical overhead parameters for embedded systems on SOTB technology

    Cortes, C., Amano, H. & Yamasaki, N., 2018 Mar 9, 2017 32nd Conference on Design of Circuits and Integrated Systems, DCIS 2017 - Proceedings. Institute of Electrical and Electronics Engineers Inc., p. 1-6 6 p. (2017 32nd Conference on Design of Circuits and Integrated Systems, DCIS 2017 - Proceedings; vol. 2017-November).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    2 Citations (Scopus)
  • Body bias optimization for variable pipelined CGRA

    Kojima, T., Ando, N., Okuhara, H., Doan, N. A. V. & Amano, H., 2017 Oct 2, 2017 27th International Conference on Field Programmable Logic and Applications, FPL 2017. Gohringer, D., Stroobandt, D., Mentens, N., Santambrogio, M. & Nurmi, J. (eds.). Institute of Electrical and Electronics Engineers Inc., 8056851. (2017 27th International Conference on Field Programmable Logic and Applications, FPL 2017).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    4 Citations (Scopus)
  • Body bias grain size exploration for a coarse grained reconfigurable accelerator

    Matsushita, Y., Okuhara, H., Masuyama, K., Fujita, Y., Kawano, R. & Amano, H., 2016 Sep 26, FPL 2016 - 26th International Conference on Field-Programmable Logic and Applications. Institute of Electrical and Electronics Engineers Inc., 7577346. (FPL 2016 - 26th International Conference on Field-Programmable Logic and Applications).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    10 Citations (Scopus)
  • Body bias control for renewable energy source with a high inner resistance

    Azegami, K., Okuhara, H. & Amano, H., 2017 Jun 12, Proceedings for 2017 IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips 2017. Institute of Electrical and Electronics Engineers Inc., 7946386

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • Body bias control for a coarse grained reconfigurable accelerator implemented with Silicon on Thin BOX technology

    Su, H., Fujita, Y. & Amano, H., 2014 Oct 16, Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014. Institute of Electrical and Electronics Engineers Inc., 6927486. (Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    14 Citations (Scopus)
  • Black-bus: A new data-transfer technique using local address on networks-on-chips

    Anjo, K., Yamada, Y., Koibuchi, M., Jouraku, A. & Amano, H., 2004 Dec 1, Proceedings - 18th International Parallel and Distributed Processing Symposium, IPDPS 2004 (Abstracts and CD-ROM). p. 115-122 8 p. (Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2004 (Abstracts and CD-ROM); vol. 18).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    8 Citations (Scopus)
  • Balanced dimension-order routing for k-ary n-cubes

    Montañana, J. M., Koibuchi, M., Matsutani, H. & Amano, H., 2009, ICPPW 2009 - The 38th International Conference Parallel Processing Workshops. p. 499-506 8 p. 5365405. (Proceedings of the International Conference on Parallel Processing Workshops).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    11 Citations (Scopus)
  • AxNoC: Low-power Approximate Network-on-Chips using Critical-Path Isolation

    Ahmed, A. B., Fujiki, D., Matsutani, H., Koibuchi, M. & Amano, H., 2018 Oct 26, 2018 12th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2018. Institute of Electrical and Electronics Engineers Inc., 8512158. (2018 12th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2018).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    19 Citations (Scopus)
  • A virtual hardware system on a dynamically reconfigurable logic device

    Shibata, Y., Uno, M., Amano, H., Furuta, K., Fujii, T. & Motomura, M., 2000, IEEE Symposium on FPGAs for Custom Computing Machines, Proceedings. Institute of Electrical and Electronics Engineers Inc., Vol. 2000-January. p. 295-296 2 p. 903423

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    11 Citations (Scopus)
  • A vertical bubble flow network using inductive-coupling for 3-D CMPs

    Matsutani, H., Take, Y., Sasaki, D., Kimura, M., Ono, Y., Nishiyama, Y., Koibuchi, M., Kuroda, T. & Amano, H., 2011, NOCS 2011: The 5th ACM/IEEE International Symposium on Networks-on-Chip. p. 49-56 8 p. (NOCS 2011: The 5th ACM/IEEE International Symposium on Networks-on-Chip).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    17 Citations (Scopus)
  • A variable-pipeline on-chip router optimized to traffic pattern

    Hirata, Y., Matsutani, H., Koibuchi, M. & Amano, H., 2010, 3rd International Workshop on Network on Chip Architectures, NoCArc 2010, in Conjunction with the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-43. p. 57-62 6 p. (3rd International Workshop on Network on Chip Architectures, NoCArc 2010, in Conjunction with the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-43).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    7 Citations (Scopus)
  • Automated Integration of High-Level Synthesis FPGA Modules with ROS2 Systems

    Leal, D. P., Sugaya, M., Amano, H. & Ohkawa, T., 2020 Dec, Proceedings - 2020 International Conference on Field-Programmable Technology, ICFPT 2020. Institute of Electrical and Electronics Engineers Inc., p. 292-293 2 p. 9415584. (Proceedings - 2020 International Conference on Field-Programmable Technology, ICFPT 2020).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • Attempt-1: A reconfigurable multiprocessor testbed

    Inoue, K., Kisuki, T., Okuno, M., Shimizu, E., Terasawa, T. & Amano, H., 1996, Field-Programmable Logic: Smart Applications, New Paradigms and Compilers - 6th International Workshop on Field-Programmable Logic and Applications, FPL 1996, Proceedings. Hartenstein, R. W. & Glesner, M. (eds.). Springer Verlag, p. 200-209 10 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 1142).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    2 Citations (Scopus)
  • A thermal management system for building block computing systems

    Fujita, Y., Usami, K. & Amano, H., 2014 Nov 6, Proceedings - 2014 IEEE 8th International Symposium on Embedded Multicore/Manycore SoCs, MCSoC 2014. Institute of Electrical and Electronics Engineers Inc., p. 165-171 7 p. 6949468. (Proceedings - 2014 IEEE 8th International Symposium on Embedded Multicore/Manycore SoCs, MCSoC 2014).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    2 Citations (Scopus)
  • A temporal correlation based port combination methodology for Networks-on-Chip on reconfigurable systems

    Wang, D., Matsutani, H., Amano, H. & Koibuchi, M., 2007 Dec 1, Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL. p. 383-388 6 p. 4380676. (Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    4 Citations (Scopus)
  • A System delay monitor exploiting automatic cell-based design flow and post-silicon calibration

    Okuhara, H., Kazami, R. & Amano, H., 2019 Oct, Proceedings - 2019 IEEE 13th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019. Institute of Electrical and Electronics Engineers Inc., p. 32-37 6 p. 8906740. (Proceedings - 2019 IEEE 13th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • A switch-tagged VLAN routing methodology for PC clusters with Ethernet

    Otsuka, T., Koibuchi, M., Kudoh, T. & Amano, H., 2006, ICPP 2006: Proceedings of the 2006 International Conference on Parallel Processing. p. 479-486 8 p. 1690652. (Proceedings of the International Conference on Parallel Processing).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    13 Citations (Scopus)
  • A study on interconnection networks of the dynamically reconfigurable processor array MuCCRA

    Kato, M., Sano, T., Yasuda, Y., Saito, Y. & Amano, H., 2009 Dec 1, Proceedings of the 2009 International Conference on Field-Programmable Technology, FPT'09. p. 415-418 4 p. 5377694. (Proceedings of the 2009 International Conference on Field-Programmable Technology, FPT'09).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    2 Citations (Scopus)
  • A study of adaptable co-processors for cyclic redundancy check on an FPGA

    Akagic, A. & Amano, H., 2012 Dec 1, FPT 2012 - 2012 International Conference on Field-Programmable Technology. p. 119-124 6 p. 6412122. (FPT 2012 - 2012 International Conference on Field-Programmable Technology).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    5 Citations (Scopus)
  • A Stdm (static time division multiplexing) switch on a multi-fpga system

    Azegami, K., Musha, K., Hironaka, K., Ben Ahmed, A., Koibuch, M., Hu, Y. & Amano, H., 2019 Oct, Proceedings - 2019 IEEE 13th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019. Institute of Electrical and Electronics Engineers Inc., p. 328-333 6 p. 8906518. (Proceedings - 2019 IEEE 13th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    6 Citations (Scopus)
  • A static scheduling system for a parallel machine (SM)2-II

    Xiao-Ping, L. & Amano, H., 1989, PARLE 1989: Parallel Architectures and Languages Europe - Parallel Languages, Proceedings. Springer Verlag, Vol. 365 LNCS. p. 118-135 18 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 365 LNCS).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    4 Citations (Scopus)
  • A speculative gather system for cool mega-array

    Uno, R., Ozaki, N., Isawa, M., Tsusaka, A., Miyajima, T. & Amano, H., 2013 Dec 1, FPT 2013 - Proceedings of the 2013 International Conference on Field Programmable Technology. p. 346-349 4 p. 6718383. (FPT 2013 - Proceedings of the 2013 International Conference on Field Programmable Technology).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    1 Citation (Scopus)
  • A scalable 3D processor by homogeneous chip stacking with inductive-coupling link

    Kohama, Y., Sugimori, Y., Saito, S., Hasegawa, Y., Sano, T., Kasuga, K., Yoshida, Y., Niitsu, K., Miura, N., Amano, H. & Kuroda, T., 2009 Nov 18, 2009 Symposium on VLSI Circuits. p. 94-95 2 p. 5205288. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    15 Citations (Scopus)
  • A scalable 3D heterogeneous multi-core processor with inductive-coupling ThruChip interface

    Miura, N., Koizumi, Y., Sasaki, E., Take, Y., Matsutani, H., Kuroda, T., Amano, H., Sakamoto, R., Namiki, M., Usami, K., Kondo, M. & Nakamura, H., 2013 Aug 15, IEEE Symposium on Low-Power and High-Speed Chips - Proceedings for 2013 COOL Chips XVI. 6547916. (IEEE Symposium on Low-Power and High-Speed Chips - Proceedings for 2013 COOL Chips XVI).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    2 Citations (Scopus)
  • A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface

    Miura, N., Koizumi, Y., Sasaki, E., Take, Y., Matsutani, H., Kuroda, T., Amano, H., Sakamoto, R., Namiki, M., Usami, K., Kondo, M. & Nakamura, H., 2013 May 24, 2013 IEEE Hot Chips 25 Symposium, HCS 2013. Institute of Electrical and Electronics Engineers Inc., 7478328. (2013 IEEE Hot Chips 25 Symposium, HCS 2013).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • Artificial intelligence of Blokus Duo on FPGA using Cyber Work Bench

    Sugimoto, N., Miyajima, T., Kuhara, T., Katuta, Y., Mitsuichi, T. & Amano, H., 2013 Dec 1, FPT 2013 - Proceedings of the 2013 International Conference on Field Programmable Technology. p. 498-501 4 p. 6718427. (FPT 2013 - Proceedings of the 2013 International Conference on Field Programmable Technology).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    3 Citations (Scopus)
  • A routing strategy for inductive-coupling based wireless 3-D NoCs by maximizing topological regularity

    Sasaki, D., Zhang, H., Matsutani, H., Koibuchi, M. & Amano, H., 2013 Dec 1, Algorithms and Architectures for Parallel Processing - 13th International Conference, ICA3PP 2013, Proceedings. PART 2 ed. p. 77-85 9 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 8286 LNCS, no. PART 2).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • A reconfigurable stochastic model simulator for analysis of parallel systems

    Yamamoto, O., Shibata, Y., Kurosawa, H. & Amano, H., 2000, Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing - 10th International Conference, FPL 2000, Proceedings. Hartenstein, R. W. & Grunbacher, H. (eds.). Springer Verlag, p. 475-484 10 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 1896).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • A reconfigurable stochastic model simulator for analysis of parallel systems

    Yamamoto, O., Shibata, Y., Kurosawa, H. & Amano, H., 2000, IEEE Symposium on FPGAs for Custom Computing Machines, Proceedings. Institute of Electrical and Electronics Engineers Inc., Vol. 2000-January. p. 291-292 2 p. 903422

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    2 Citations (Scopus)
  • A reconfigurable sensor-data processing system for personal robots

    Nukata, K., Shibata, Y., Amano, H. & Anzai, Y., 1997, Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Springer Verlag, Vol. 1304. p. 491-500 10 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 1304).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    2 Citations (Scopus)
  • A rapid optimization method for visual indirect SLAM using a subset of feature points

    Kazami, R. & Amano, H., 2019 Nov, Proceedings - 2019 7th International Symposium on Computing and Networking Workshops, CANDARW 2019. Institute of Electrical and Electronics Engineers Inc., p. 275-279 5 p. 8951546. (Proceedings - 2019 7th International Symposium on Computing and Networking Workshops, CANDARW 2019).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • A prototype chip of multicontext FPGA with DRAM for virtual hardware

    Kawakami, D., Shibata, Y. & Amano, H., 2001 Jan 1, Proceedings of the ASP-DAC 2001: Asia and South Pacific Design Automation Conference 2001. Institute of Electrical and Electronics Engineers Inc., p. 17-18 2 p. 913267. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; vol. 2001-January).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    7 Citations (Scopus)
  • A proposal of thread virtualization environment for cell broadband engine

    Yamada, M., Nishikawa, Y., Yoshimi, M. & Amano, H., 2010, Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Systems, PDCS 2010. p. 32-39 8 p. (Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Systems).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    2 Citations (Scopus)
  • A programming environment for multi-FPGA systems based on CyberWorkBench: An integrated design tool

    Suzuki, H., Takahashi, W., Wakabayashi, K. & Amano, H., 2021 Jun 21, Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, HEART 2021. Association for Computing Machinery, 5. (ACM International Conference Proceeding Series).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • A Preliminary evaluation of building block computing systems

    Terashima, S., Kojima, T., Okuhara, H., Musha, K., Amano, H., Sakamoto, R., Kondo, M. & Namiki, M., 2019 Oct, Proceedings - 2019 IEEE 13th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019. Institute of Electrical and Electronics Engineers Inc., p. 312-319 8 p. 8906777. (Proceedings - 2019 IEEE 13th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution