Hideharu Amano

Research output

Research output per year 1983 2003 2005 2007 2008 2009 2010 2011 2012 2013 2015 2016 2017 2018 2019 2020 2021 2023

• 361 Conference contribution
• 118 Article
• 21 Paper
• 14 Editorial
• 26 More
  • 13 Conference article
  • 10 Chapter
  • 3 Review article

Research output per year

Research output per year

Search results

• Conference contribution

  NDL: A LANGUAGE FOR SOLVING SCIENTIFIC PROBLEMS ON MIMD MACHINES.

  Kudoh, T., Amano, H., Boku, T. & Aiso, H., 1985 Dec 1, Unknown Host Publication Title. IEEE, p. 55-64 10 p.

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Data transfer 100%
  • Process control 90%
  • Computer programming languages 89%
  • Networks (circuits) 54%
  • Communication 49%
  3 Citations (Scopus)

• Non-Volatile Coarse Grained Reconfigurable Array Enabling Two-step Store Control for Energy Minimization

  Usami, K., Akiba, S., Amano, H., Ikezoe, T., Hiraga, K., Suzuki, K. & Kanda, Y., 2020 Apr, IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2020 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 9097630. (IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2020 - Proceedings).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Inventory control 100%
  • Flip flop circuits 89%
  • Microcontrollers 25%
  • Internet of things 21%
  • Image processing 20%
  3 Citations (Scopus)

• On-chip decentralized routers with balanced pipelines for avoiding interconnect bottleneck

  Yasudo, R., Matsutani, H., Koibuchi, M., Amano, H. & Nakamura, T., 2015 Sept 28, Proceedings - 2015 9th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2015. Marculescu, D., Ivanov, A., Pande, P. P. & Flich, J. (eds.). Association for Computing Machinery, Inc, 2817280. (Proceedings - 2015 9th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2015).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Routers 100%
  • Pipelines 79%
  • Wire 22%
  1 Citation (Scopus)

• On-chip detection methodology for break-even time of power gated function units

  Usami, K., Goto, Y., Matsunaga, K., Koyama, S., Ikebuchi, D., Amano, H. & Nakamura, H., 2011 Sept 19, IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011. p. 241-246 6 p. 5993643. (Proceedings of the International Symposium on Low Power Electronics and Design).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Program processors 100%
  • Energy conservation 93%
  • Switches 84%
  • Networks (circuits) 64%
  • Temperature 47%
  17 Citations (Scopus)

• On-the-fly data compression/decompression mechanism with ExpEther

  Shimura, H., Mitsuishi, T., Amano, H., Kan, M. & Yoshikawa, T., 2017 Jan 13, Proceedings - 2016 4th International Symposium on Computing and Networking, CANDAR 2016. Institute of Electrical and Electronics Engineers Inc., p. 112-118 7 p. 7818601. (Proceedings - 2016 4th International Symposium on Computing and Networking, CANDAR 2016).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Data compression 100%
  • Ethernet 93%
  • Graphics processing unit 64%
  • Bandwidth 28%
  • Virtualization 24%
  1 Citation (Scopus)

• On-the-fly sending: A low latency high bandwidth message transfer mechanism

  Tanabe, N., Yamamoto, J., Nishi, H., Kudoh, T., Hamada, Y., Nakajo, H. & Amano, H., 2000, Proceedings - International Symposium on Parallel Architectures, Algorithms, and Networks, I-SPAN 2000. Sudborough, H., Monien, B. & Hsu, D. F. (eds.). Institute of Electrical and Electronics Engineers Inc., p. 186-193 8 p. (Proceedings - International Symposium on Parallel Architectures, Algorithms, and Networks, I-SPAN 2000).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Latency 100%
  • Bandwidth 78%
  • Interfaces (computer) 72%
  • Architecture 33%
  • Personal Computer 20%

• Optimal switching time to minimize store energy in MTJ-based flip-flops under process and temperature variations

  Usami, K., Yokoyama, D., Kamei, A. & Amano, H., 2022, 2022 IEEE Nordic Circuits and Systems Conference, NORCAS 2022 - Proceedings. Nurmi, J., Wisland, D. T., Aunet, S. & Kjelgaard, K. (eds.). Institute of Electrical and Electronics Engineers Inc., (2022 IEEE Nordic Circuits and Systems Conference, NORCAS 2022 - Proceedings).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Flip flop circuits 100%
  • Normal distribution 47%
  • Temperature 34%

• Optimized core-links for low-latency NoCs

  Kawano, R., Tade, S., Fujiwara, I., Matsutani, H., Amano, H. & Koibuchi, M., 2015, Proceedings - 23rd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2015. Lilius, J., Daneshtalab, M., Brorsson, M., Leppanen, V. & Aldinucci, M. (eds.). Institute of Electrical and Electronics Engineers Inc., p. 172-176 5 p. 7092716. (Proceedings - 23rd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2015).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Routers 100%
  • Topology 88%
  • Small-world networks 36%
  • Packet networks 30%
  • Network-on-chip 29%

• Optimizing Application Mapping for Multi-FPGA Systems with Multi-ejection STDM Switches

  Ito, K., Yasudo, R. & Amano, H., 2022, Proceedings - 2022 32nd International Conference on Field-Programmable Logic and Applications, FPL 2022. Institute of Electrical and Electronics Engineers Inc., p. 143-147 5 p. (Proceedings - 2022 32nd International Conference on Field-Programmable Logic and Applications, FPL 2022).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Field Programmable Gate Array 100%
  • Multiplexing 95%
  • time division multiplexing 86%
  • Time division multiplexing 80%
  • Switch 68%

• Order/Radix Problem: Towards Low End-to-End Latency Interconnection Networks

  Yasudo, R., Koibuchi, M., Nakano, K., Matsutani, H. & Amano, H., 2017 Sept 1, Proceedings - 46th International Conference on Parallel Processing, ICPP 2017. Institute of Electrical and Electronics Engineers Inc., p. 322-331 10 p. 8025306. (Proceedings of the International Conference on Parallel Processing).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Latency 100%
  • Interconnection Networks 92%
  • Switch 82%
  • Switches 54%
  • Path Length 32%
  2 Citations (Scopus)

• Overwrite configuration technique in multicast configuration scheme for dynamically reconfigurable processor arrays

  Tsutsumi, S., Tunbunheng, V., Hasegawa, Y., Parimala, A., Nakamura, T., Nishimura, T. & Amano, H., 2007, ICFPT 2007 - International Conference on Field Programmable Technology. p. 273-276 4 p. 4439264. (ICFPT 2007 - International Conference on Field Programmable Technology).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Parallel processing systems 100%
  • Power and Energy 57%
  • Data transfer 49%
  • Scheduling algorithms 47%
  • Energy utilization 34%
  4 Citations (Scopus)

• Parallel Implementation of CNN on Multi-FPGA Cluster

  Fukushima, Y., Iizuka, K. & Amano, H., 2021, Proceedings - 2021 IEEE 14th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2021. Institute of Electrical and Electronics Engineers Inc., p. 77-83 7 p. (Proceedings - 2021 IEEE 14th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2021).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Edge computing 100%
  • Field programmable gate arrays (FPGA) 99%
  • Pipelines 61%
  • Image recognition 46%
  • Open source software 45%
  2 Citations (Scopus)

• Partially reconfigurable flux calculation scheme in advection term computation

  Talip, M. S. A., Akamine, T., Hatto, M., Osana, Y., Fujita, N. & Amano, H., 2013 Dec 1, FPT 2013 - Proceedings of the 2013 International Conference on Field Programmable Technology. p. 382-385 4 p. 6718393. (FPT 2013 - Proceedings of the 2013 International Conference on Field Programmable Technology).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Advection 100%
  • Field programmable gate arrays (FPGA) 64%
  • Fluxes 63%
  • Aerodynamics 62%
  • Reconfigurable hardware 51%
  2 Citations (Scopus)

• Performance, cost, and energy evaluation of fat H-tree: A cost-efficient tree-based on-chip network

  Matsutani, H., Koibuchi, M. & Amano, H., 2007 Sept 24, Proceedings - 21st International Parallel and Distributed Processing Symposium, IPDPS 2007; Abstracts and CD-ROM. 4227999. (Proceedings - 21st International Parallel and Distributed Processing Symposium, IPDPS 2007; Abstracts and CD-ROM).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Network on chip 100%
  • Performance Evaluation 66%
  • Oils and fats 58%
  • Network-on-chip 56%
  • Evaluation 36%
  22 Citations (Scopus)

• Performance, cost, and power evaluations of on-chip network topologies in FPGAs

  In, S., Matsutani, H., Koibuchi, M., Wang, D. & Amano, H., 2010 Jul 20, Proceedings of the 9th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2010. p. 181-189 9 p. (Proceedings of the 9th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2010).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Field Programmable Gate Array 100%
  • Performance Evaluation 84%
  • Network Topology 83%
  • Chip 81%
  • Network-on-chip 71%

• Performance/cost trade-off evaluation for the DCT implementation on the dynamically reconfigurable processor

  Tuan, V. M., Hasegawa, Y., Katsura, N. & Amano, H., 2006 Jan 1, Reconfigurable Computing: Architectures and Applications - Second International Workshop, ARC 2006, Revised Selected Papers. Springer Verlag, p. 115-121 7 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 3985 LNCS).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Discrete Cosine Transform 100%
  • Discrete cosine transforms 74%
  • Trade-offs 67%
  • Energy dissipation 56%
  • Clocks 56%
  1 Citation (Scopus)

• Performance analysis for the arbitor of IEEE standard backplane bus Futurebus/Futurebus+

  Yamamoto, O., Takemoto, T., Kimura, T. & Amano, H., 1993 Jan 1, Proc IEEE 1993 Pac Rim Conf Commun Comput Signal Process. Publ by IEEE, p. 386-389 4 p. (Proc IEEE 1993 Pac Rim Conf Commun Comput Signal Process).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • IEEE Standards 100%
  1 Citation (Scopus)

• Performance analysis of clearspeed's CSX600 interconnects

  Nishikawa, Y., Koibuchi, M., Yoshimi, M., Shitara, A., Miura, K. & Amano, H., 2009 Nov 19, Proceedings - 2009 IEEE International Symposium on Parallel and Distributed Processing with Applications, ISPA 2009. p. 203-210 8 p. 5207934. (Proceedings - 2009 IEEE International Symposium on Parallel and Distributed Processing with Applications, ISPA 2009).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Bandwidth 100%
  • Data transfer 80%
  • Topology 54%
  • Data storage equipment 48%
  1 Citation (Scopus)

• Performance analysis of fully-adaptable CRC accelerators on an FPGA

  Akagic, A. & Amano, H., 2012 Dec 12, Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012. p. 575-578 4 p. 6339374. (Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Particle accelerators 100%
  • Redundancy 83%
  • Field programmable gate arrays (FPGA) 80%
  • Throughput 68%

• Performance and cost analysis of time-multiplexed execution on the dynamically reconfigurable processor

  Amano, H., Abe, S., Hasegawa, Y., Deguchi, K. & Suzuki, M., 2005 Dec 1, Proceedings - 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2005. p. 315-316 2 p. 1508569. (Proceedings - 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2005; vol. 2005).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Costs 100%
  8 Citations (Scopus)

• Performance and power analysis of time-multiplexed execution on dynamically reconfigurable processor

  Hasegawa, Y., Abe, S., Kurotaki, S., Tuan, V. M., Katsura, N., Nakamura, T., Nishimura, T. & Amano, H., 2006, 20th International Parallel and Distributed Processing Symposium, IPDPS 2006. IEEE Computer Society, 1639431. (20th International Parallel and Distributed Processing Symposium, IPDPS 2006; vol. 2006).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Energy dissipation 100%
  • Electronic equipment 98%
  • Networks (circuits) 64%

• Performance Estimation for Exascale Reconfigurable Dataflow Platforms

  Yasudo, R., Coutinho, J., Varbanescu, A., Luk, W., Amano, H. & Becker, T., 2018 Dec, Proceedings - 2018 International Conference on Field-Programmable Technology, FPT 2018. Institute of Electrical and Electronics Engineers Inc., p. 317-320 4 p. 8742283. (Proceedings - 2018 International Conference on Field-Programmable Technology, FPT 2018).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Particle accelerators 100%
  • Analytical models 41%
  • Calibration 37%
  8 Citations (Scopus)

• Performance evaluation of 3-dimensional MIN with cache consistency maintenance mechanism

  Tanabe, Y., Midorikawa, T., Shiraishi, D., Shigeno, M., Hanawa, T. & Amano, H., 2003, Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA 2003. Arabnia, H. R., Mun, Y., Arabnia, H. R. & Mun, Y. (eds.). p. 1148-1154 7 p. (Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications; vol. 3).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Throughput 100%
  • Bandwidth 90%
  1 Citation (Scopus)

• Performance evaluation of an FPGA-based biochemical simulator ReCSiP

  Osana, Y., Yoshimi, M., Iwaoka, Y., Kojima, T., Nishikawa, Y., Funahashi, A., Hiroi, N., Kitano, H., Amano, H., Shibata, Y. & Iwanaga, N., 2006 Dec 1, Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL. p. 845-850 6 p. 4101089. (Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Field Programmable Gate Array 100%
  • Performance Evaluation 84%
  • Simulator 81%
  • Field programmable gate arrays (FPGA) 51%
  • Reaction Mechanism 49%
  4 Citations (Scopus)

• Performance Evaluation of a Prototype of RHiNET-2: A Network-based Distributed Parallel Computing System

  Otsuka, T., Watanabe, K., Tsuchiya, J. I., Harada, H., Yamamoto, J., Nishi, H., Kudoh, T. & Amano, H., 2003 Dec 1, 21st IASTED International Multi-Conference on Applied Informatics. p. 738-743 6 p. (IASTED International Multi-Conference on Applied Informatics; vol. 21).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Parallel processing systems 100%
  • Local area networks 96%
  5 Citations (Scopus)

• Performance evaluation of instruction set architecture of MBP-light: A distributed memory controller for a large scale multiprocessor

  Suzuki, N. & Amano, H., 2003 Dec 1, Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA 2003. Arabnia, H. R., Mun, Y., Arabnia, H. R. & Mun, Y. (eds.). p. 1155-1161 7 p. (Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications; vol. 3).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Data storage equipment 100%
  • Controllers 88%
  • Reduced instruction set computing 68%

• Performance evaluation of multiple lookup tables algorithms for generating CRC on an FPGA

  Akagić, A. & Amano, H., 2011 Aug 23, Proceedings of 2011 1st International Symposium on Access Spaces, ISAS 2011. p. 164-169 6 p. 5960941. (Proceedings of 2011 1st International Symposium on Access Spaces, ISAS 2011).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Table lookup 100%
  • Field programmable gate arrays (FPGA) 67%
  • Throughput 57%
  • Clocks 17%
  • Computer hardware 12%
  5 Citations (Scopus)

• Performance Evaluation of PEACH3: Field-Programmable Gate Array Switch for Tightly Coupled Accelerators

  Kaneda, T., Sakai, R., Nishikawa, N., Hanawa, T., Tsuruta, C. & Amano, H., 2017 Jun 7, Proceedings of the 8th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, HEART 2017. Association for Computing Machinery, 9. (ACM International Conference Proceeding Series).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Particle accelerators 100%
  • Field programmable gate arrays (FPGA) 80%
  • Switches 70%
  • Graphics processing unit 68%
  • Communication 49%

• Performance evaluation of power-aware multi-tree ethernet for HPC interconnects

  Koibuchi, M., Watanabe, T., Minamihata, A., Nakao, M., Hiroyasu, T., Matsutani, H. & Amano, H., 2011, Proceedings - 2011 2nd International Conference on Networking and Computing, ICNC 2011. p. 50-57 8 p. 6131793. (Proceedings - 2011 2nd International Conference on Networking and Computing, ICNC 2011).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Ethernet 100%
  • Topology 37%
  • Electric power utilization 30%
  • Switches 20%
  • Agglomeration 12%
  1 Citation (Scopus)

• Performance evaluation of RHiNET 2/NI: A network interface for distributed parallel computing systems

  Watanabe, K., Otsuka, T., Tsuchiya, J. I., Amano, H., Harada, H., Yamamoto, J., Nishi, H. & Kudoh, T., 2003 Dec 1, Proceedings - CCGrid 2003: 3rd IEEE/ACM International Symposium on Cluster Computing and the Grid. p. 318-325 8 p. 1199383. (Proceedings - CCGrid 2003: 3rd IEEE/ACM International Symposium on Cluster Computing and the Grid).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Distributed Computing 100%
  • Performance Evaluation 95%
  • Parallel Computing 93%
  • Parallel processing systems 73%
  • Interfaces (computer) 67%
  10 Citations (Scopus)

• Performance evaluation of routing algorithms in RHiNET-2 cluster

  Koibuchi, M., Watanabe, K., Kono, K., Jouraku, A. & Amano, H., 2003 Jan 1, Proceedings - IEEE International Conference on Cluster Computing, CLUSTER 2003. Institute of Electrical and Electronics Engineers Inc., p. 395-402 8 p. 1253339. (Proceedings - IEEE International Conference on Cluster Computing, ICCC; vol. 2003-January).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Routing algorithms 100%
  • HPSS 87%
  • Synchronization 78%
  • Bandwidth 61%
  • Interfaces (computer) 46%
  15 Citations (Scopus)

• Performance evaluation of WASMII: A data driven computer on a virtual hardware

  Ling, X. P. & Amano, H., 1993 Jan 1, PARLE 1993 - Parallel Architectures and Languages Europe - 5th International PARLE Conference, Proceedings. Bode, A., Reeve, M. & Wolf, G. (eds.). Springer Verlag, p. 610-621 12 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 694 LNCS).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Performance Evaluation 100%
  • Hardware 92%
  • Data-driven 85%
  • Random access storage 82%
  • Chip 64%
  4 Citations (Scopus)

• Performance evaluation on low-latency communication mechanism of DIMMnet-2

  Kitamura, A., Miyabe, Y., Miyashiro, T., Tanabe, N., Nakajo, H. & Amano, H., 2007 Dec 1, Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2007. p. 57-62 6 p. (Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Systems).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Interfaces (computer) 100%
  • Communication 70%
  • Field programmable gate arrays (FPGA) 28%
  • Bandwidth 22%
  • Data storage equipment 21%
  3 Citations (Scopus)

• Performance improvement methodology for ClearSpeed's CSX600

  Nishikawa, Y., Koibuchi, M., Yoshimi, M., Miura, K. & Amano, H., 2007 Dec 1, 2007 International Conference on Parallel Processing, ICPP. 4343884. (Proceedings of the International Conference on Parallel Processing).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Data storage equipment 100%
  • Bandwidth 51%
  • Coprocessor 50%
  • Tuning 31%
  2 Citations (Scopus)

• Performance Prediction for Large-Scale Heterogeneous Platforms

  Yasudo, R., Varbanescu, A. L., Coutinho, J. G. F., Luk, W. & Amano, H., 2018 Sept 7, Proceedings - 26th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2018. Institute of Electrical and Electronics Engineers Inc., p. 220 1 p. 8457669. (Proceedings - 26th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2018).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Statistical Models 100%

• Power Analysis of Directly-connected FPGA Clusters

  Iizuka, K., Takagi, H., Kamei, A., Hironaka, K. & Amano, H., 2022, 25th IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL Chips 2022 - Proceedings. Institute of Electrical and Electronics Engineers Inc., (25th IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL Chips 2022 - Proceedings).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Field programmable gate arrays (FPGA) 100%
  • Electric power utilization 90%
  • Agglomeration 35%
  • Clocks 34%
  • Logic design 26%
  1 Citation (Scopus)

• Power centric application mapping for dynamically reconfigurable processor array with Dual Vdd and Dual Vth

  Hironaka, K. & Amano, H., 2011 Dec 1, Proceedings - 2011 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2011. p. 404-409 6 p. 6128611. (Proceedings - 2011 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2011).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Parallel processing systems 100%
  2 Citations (Scopus)

• Power Consumption Reduction Method and Edge Offload Server for Multiple Robots

  Natsuho, S., Ohkawa, T., Amano, H. & Sugaya, M., 2022, Edge Computing - EDGE 2021 - 5th International Conference, Held as Part of the Services Conference Federation, SCF 2021, Proceedings. Zhang, L-J. (ed.). Springer Science and Business Media Deutschland GmbH, p. 1-19 19 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 12990 LNCS).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Power Consumption 100%
  • Robot 75%
  • Reduction Method 69%
  • Server 65%
  • Electric power utilization 45%

• Power Optimization Considering the Chip Temperature of Low Power Reconfigurable Accelerator CMA-SOTB

  Fujita, Y., Okuhara, H., Masuyama, K. & Amano, H., 2016 Mar 2, Proceedings - 2015 3rd International Symposium on Computing and Networking, CANDAR 2015. Institute of Electrical and Electronics Engineers Inc., p. 21-29 9 p. 7424265

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Silicon 100%
  • Accelerator 98%
  • Chip 90%
  • Bias voltage 88%
  • Voltage 80%
  5 Citations (Scopus)

• Power reduction techniques for dynamically reconfigurable processor arrays

  Nishimura, T., Hirai, K., Saito, Y., Nakamura, T., Hasegawa, Y., Tsutsusmi, S., Tunbunheng, V. & Amano, H., 2008 Nov 3, Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL. p. 305-310 6 p. 4629949. (Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Parallel processing systems 100%
  • Electric power utilization 48%
  • Array processing 42%
  • Computer hardware 19%
  18 Citations (Scopus)

• Practical implementation of a network-based Stochastic biochemical simulation system on an FPGA

  Yoshimi, M., Nishikawa, Y., Osana, Y., Funahashi, A., Hiroi, N., Shibata, Y., Yamada, H., Kitano, H. & Amano, H., 2008, Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL. p. 663-666 4 p. 4630034. (Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Field programmable gate arrays (FPGA) 100%
  • Scalability 32%
  • Simulators 29%
  • Throughput 28%
  • Computer hardware 23%
  4 Citations (Scopus)

• Prediction router: Yet another low latency on-chip router architecture

  Matsutani, H., Koibuchi, M., Amano, H. & Yoshinaga, T., 2009, Proceedings - 15th International Symposium on High-Performance Computer Architecture, HPCA - 15 2009. IEEE Computer Society, p. 367-378 12 p. 4798274. (Proceedings - International Symposium on High-Performance Computer Architecture).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Routers 100%
  • Communication 15%
  • Switches 14%
  • Computer hardware 12%
  • Oils and fats 12%
  72 Citations (Scopus)

• Preliminary evaluation of batch-learning self-organizing map algorithm on a graphic processor

  Shitara, A., Nishikawa, Y., Yoshimi, M., Abe, T., Ikemura, T. & Amano, H., 2010, Proceedings of the 9th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2010. Acta Press, p. 96-104 9 p. (Proceedings of the 9th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2010).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Graphics Processors 100%
  • Self-organizing Map 79%
  • Self organizing maps 60%
  • Batch 59%
  • Learning 48%

• Preliminary evaluations of a FPGA-based-prototype of DIMMnet-2 network interface

  Tanabe, N., Kitamura, A., Miyashiro, T., Miyabe, Y., Izawa, T., Hamada, Y., Nakajo, H. & Amano, H., 2005, IWIA 2005: Innovative Architecture for Future Generation High-Performance Processors and Systems. IEEE Computer Society, p. 9-17 9 p. 1587833. (Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems; vol. 2005).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Interfaces (computer) 100%
  • Field programmable gate arrays (FPGA) 86%
  • Data storage equipment 32%
  • Application specific integrated circuits 28%
  3 Citations (Scopus)

• Proposal of auto MPI expansion tool for cell broadband engine cluster

  Nakahama, T., Yamada, M., Yoshimi, M. & Amano, H., 2011, Proceedings - 2011 2nd International Conference on Networking and Computing, ICNC 2011. p. 166-172 7 p. 6131802. (Proceedings - 2011 2nd International Conference on Networking and Computing, ICNC 2011).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Engines 100%
  • Parallel programming 46%
  • Monte Carlo methods 41%
  • Particle accelerators 39%
  • Application programming interfaces (API) 37%

• Prototyping on using a DIMM slot as a high-performance I/O interface

  Tanabe, N., Hamada, Y., Mitsuhashi, A., Nakajo, H., Yamamoto, J., Imashiro, H., Kudoh, T. & Amano, H., 2003, Innovative Architecture for Future Generation High-Performance Processors and Systems, IWIA 2003. Veidenbaum, A. & Joe, K. (eds.). IEEE Computer Society, p. 108-116 9 p. 1262788. (Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems; vol. 2003-January).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Interfaces (computer) 100%
  • Bandwidth 66%
  • Servers 38%
  3 Citations (Scopus)

• Randomizing Packet Memory Networks for Low-Latency Processor-Memory Communication

  Fujiki, D., Matsutani, H., Koibuchi, M. & Amano, H., 2016 Mar 31, Proceedings - 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2016. Cotronis, Y., Daneshtalab, M. & Papadopoulos, G. A. (eds.). Institute of Electrical and Electronics Engineers Inc., p. 168-175 8 p. 7445327. (Proceedings - 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2016).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Latency 100%
  • Communication 69%
  • Data storage equipment 46%
  • Random Networks 19%
  • Topology 15%
  5 Citations (Scopus)

• Real chip evaluation of a low power CGRA with optimized application mapping

  Kojima, T., Ando, N., Matshushita, Y., Okuhara, H., Doan, N. A. V. & Amano, H., 2018 Jun 20, Proceedings of the 9th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, HEART 2018. Association for Computing Machinery, a13. (ACM International Conference Proceeding Series).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Reconfigurable architectures 100%
  • Pipelines 28%
  • Electric power utilization 27%
  • Throughput 13%
  7 Citations (Scopus)

• Real chip performance evaluation on through chip interface IP for renesas SOTB 65nm process

  Kayashima, H., Kojima, T., Okuhara, H., Shidei, T. & Amano, H., 2019 Nov, Proceedings - 2019 7th International Symposium on Computing and Networking Workshops, CANDARW 2019. Institute of Electrical and Electronics Engineers Inc., p. 269-274 6 p. 8951550. (Proceedings - 2019 7th International Symposium on Computing and Networking Workshops, CANDARW 2019).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Particle accelerators 100%
  • Electric power systems 83%
  • Transmitters 82%
  • Data transfer 50%
  • Towers 45%
  1 Citation (Scopus)

• Reconfigurable out-of-order mechanism generator for unstructured grid computation in computational fluid dynamics

  Akamine, T., Inakagata, K., Osana, Y., Fujita, N. & Amano, H., 2012 Dec 12, Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012. p. 136-142 7 p. 6339277. (Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012).

  Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  • Computational fluid dynamics 100%
  • Subroutines 74%
  • Particle accelerators 67%
  • Hazards 59%
  • Field programmable gate arrays (FPGA) 54%
  5 Citations (Scopus)