• 2520 Citations
  • 23 h-Index
1983 …2020

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2017

Acceleration of the aggregation process in a Hall-thruster simulation using Intel FPGA SDK for OpenCL

Noda, H., Sakai, R., Miyajima, T., Fujita, N. & Amano, H., 2017 Jun 7, Proceedings of the 8th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, HEART 2017. Association for Computing Machinery, 20

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Accelerator-in-switch: A framework for tightly coupled switching hub and an accelerator with FPGA

Tsuruta, C., Kaneda, T., Nishikawa, N. & Amano, H., 2017 Oct 2, 2017 27th International Conference on Field Programmable Logic and Applications, FPL 2017. Institute of Electrical and Electronics Engineers Inc., 8056846

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

An inductive-coupling bus with collision detection scheme using magnetic field variation for 3-D network-on-chips

Kadomoto, J., Miyata, T., Amano, H. & Kuroda, T., 2017 Feb 6, 2016 IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 - Proceedings. Institute of Electrical and Electronics Engineers Inc., p. 41-44 4 p. 7844130

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Body bias control for renewable energy source with a high inner resistance

Azegami, K., Okuhara, H. & Amano, H., 2017 Jun 12, Proceedings for 2017 IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips 2017. Institute of Electrical and Electronics Engineers Inc., 7946386

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Body bias optimization for variable pipelined CGRA

Kojima, T., Ando, N., Okuhara, H., Doan, N. A. V. & Amano, H., 2017 Oct 2, 2017 27th International Conference on Field Programmable Logic and Applications, FPL 2017. Institute of Electrical and Electronics Engineers Inc., 8056851

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

High-Bandwidth Low-Latency Approximate Interconnection Networks

Fujiki, D., Ishii, K., Fujiwara, I., Matsutani, H., Amano, H., Casanova, H. & Koibuchi, M., 2017 May 5, Proceedings - 2017 IEEE 23rd Symposium on High Performance Computer Architecture, HPCA 2017. IEEE Computer Society, p. 469-480 12 p. 7920848

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Citations (Scopus)

Implementation of bitsliced AES encryption on CUDA-Enabled GPU

Nishikawa, N., Amano, H. & Iwai, K., 2017, Network and System Security - 11th International Conference, NSS 2017, Proceedings. Springer Verlag, Vol. 10394 LNCS. p. 273-287 15 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 10394 LNCS).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Implementing breadth-first search on a compact supercomputer suiren

Mitsuishi, T., Kaneda, T., Torii, S. & Amano, H., 2017 Jan 13, Proceedings - 2016 4th International Symposium on Computing and Networking, CANDAR 2016. Institute of Electrical and Electronics Engineers Inc., p. 395-401 7 p. 7818645

Research output: Chapter in Book/Report/Conference proceedingConference contribution

In-switch approximate processing: Delayed tasks management for MapReduce applications

Mitsuzuka, K., Hayashi, A., Koibuchi, M., Amano, H. & Matsutani, H., 2017 Oct 2, 2017 27th International Conference on Field Programmable Logic and Applications, FPL 2017. Institute of Electrical and Electronics Engineers Inc., 8056802

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Level-shifter-less approach for multi-VDD design to use body bias control in FD-SOI

Usami, K., Kogure, S., Yoshida, Y., Magasaki, R. & Amano, H., 2017 Dec 13, 25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017 - Proceedings. IEEE Computer Society, 8203473

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Leveraging asymmetric body bias control for low power LSI design

Okuhara, H., Ahmed, A. B., Kuhn, J. M. & Amano, H., 2017 Jun 12, Proceedings for 2017 IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips 2017. Institute of Electrical and Electronics Engineers Inc., 7946379

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

LOREN: A scalable routing method for layout-conscious random topologies

Kawano, R., Nakahara, H., Fujiwara, I., Matsutani, H., Koibuchi, M. & Amano, H., 2017 Jan 13, Proceedings - 2016 4th International Symposium on Computing and Networking, CANDAR 2016. Institute of Electrical and Electronics Engineers Inc., p. 9-18 10 p. 7818589

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Namacha: A software development environment for a multi-chip convolutional network accelerator

Ohkubo, T., Takata, R., Sakamoto, R., Kondo, M. & Amano, H., 2017, Proceedings of the 32nd International Conference on Computers and Their Applications, CATA 2017. The International Society for Computers and Their Applications (ISCA), p. 101-106 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

On-the-fly data compression/decompression mechanism with ExpEther

Shimura, H., Mitsuishi, T., Amano, H., Kan, M. & Yoshikawa, T., 2017 Jan 13, Proceedings - 2016 4th International Symposium on Computing and Networking, CANDAR 2016. Institute of Electrical and Electronics Engineers Inc., p. 112-118 7 p. 7818601

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Order/Radix Problem: Towards Low End-to-End Latency Interconnection Networks

Yasudo, R., Koibuchi, M., Nakano, K., Matsutani, H. & Amano, H., 2017 Sep 1, Proceedings - 46th International Conference on Parallel Processing, ICPP 2017. Institute of Electrical and Electronics Engineers Inc., p. 322-331 10 p. 8025306

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Performance Evaluation of PEACH3: Field-Programmable Gate Array Switch for Tightly Coupled Accelerators

Kaneda, T., Sakai, R., Nishikawa, N., Hanawa, T., Tsuruta, C. & Amano, H., 2017 Jun 7, Proceedings of the 8th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, HEART 2017. Association for Computing Machinery, 9

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Switching region analysis for SOTB technology

Cortes, C. & Amano, H., 2017 Jun 27, 2017 International Caribbean Conference on Devices, Circuits and Systems, ICCDCS 2017. Institute of Electrical and Electronics Engineers Inc., p. 33-36 4 p. 7959717

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Towards tightly-coupled datacenter with free-space optical links

Hu, Y., Matsutani, H., Hara, H., Amano, H., Fujiwara, I. & Koibuchi, M., 2017 Sep 17, 2017 International Conference on Cloud and Big Data Computing, ICCBDC 2017. Association for Computing Machinery, p. 33-39 7 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Trax Solver on Zynq using incremental update algorithm

Nakahara, H., Ohkubo, T., Shimura, H., Sakai, R., Tsuruta, C., Kaneda, T. & Amano, H., 2017 May 15, Proceedings of the 2016 International Conference on Field-Programmable Technology, FPT 2016. Institute of Electrical and Electronics Engineers Inc., p. 323-326 4 p. 7929564

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Variable pipeline structure for coarse grained reconfigurable array CMA

Ando, N., Masuyama, K., Okuhara, H. & Amano, H., 2017 May 15, Proceedings of the 2016 International Conference on Field-Programmable Technology, FPT 2016. Institute of Electrical and Electronics Engineers Inc., p. 217-220 4 p. 7929537

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Vertical packet switching elevator network using inductive coupling ThruChip interface

Nomura, A., Matsutani, H., Kuroda, T., Kadomoto, J., Matsushita, Y. & Amano, H., 2017 Jan 13, Proceedings - 2016 4th International Symposium on Computing and Networking, CANDAR 2016. Institute of Electrical and Electronics Engineers Inc., p. 195-201 7 p. 7818613

Research output: Chapter in Book/Report/Conference proceedingConference contribution

XYZ-Randomization using TSVs for low-latency energy efficient 3D-NoCs

Nakahara, H., Doan, N. A. V., Yasudo, R. & Amano, H., 2017 Oct 19, 2017 11th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2017. Association for Computing Machinery, Inc, 17

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)
2016

A 297mops/0.4mw ultra low power coarse-grained reconfigurable accelerator CMA-SOTB-2

Masuyama, K., Fujita, Y., Okuhara, H. & Amano, H., 2016 Jan 25, 2015 International Conference on ReConFigurable Computing and FPGAs, ReConFig 2015. Institute of Electrical and Electronics Engineers Inc., 7393280

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Acceleration of Full-PIC Simulation on a CPU-FPGA Tightly Coupled Environment

Sakai, R., Sugimoto, N., Amano, H., Miyajima, T. & Fujita, N., 2016 Dec 5, Proceedings - IEEE 10th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2016. Institute of Electrical and Electronics Engineers Inc., p. 8-14 7 p. 7774414

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

ACRO: Assignment of channels in reverse order to make arbitrary routing deadlock-free

Kawano, R., Nakahara, H., Tade, S., Fujiwara, I., Matsutani, H., Koibuchi, M. & Amano, H., 2016 Aug 23, 2016 IEEE/ACIS 15th International Conference on Computer and Information Science, ICIS 2016 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 7550818

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

A perpetuum mobile 32bit CPU on 65nm SOTB CMOS technology with reverse-body-bias assisted sleep mode

Kamohara, S., Sugii, N., Ishibashi, K., Usami, K., Amano, H., Kobayashi, K. & Pham, C. K., 2016 May 25, 2014 IEEE Hot Chips 26 Symposium, HCS 2014. Institute of Electrical and Electronics Engineers Inc., 7478838

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface

Miura, N., Koizumi, Y., Sasaki, E., Take, Y., Matsutani, H., Kuroda, T., Amano, H., Sakamoto, R., Namiki, M., Usami, K., Kondo, M. & Nakamura, H., 2016 May 24, 2013 IEEE Hot Chips 25 Symposium, HCS 2013. Institute of Electrical and Electronics Engineers Inc., 7478328

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Body bias grain size exploration for a coarse grained reconfigurable accelerator

Matsushita, Y., Okuhara, H., Masuyama, K., Fujita, Y., Kawano, R. & Amano, H., 2016 Sep 26, FPL 2016 - 26th International Conference on Field-Programmable Logic and Applications. Institute of Electrical and Electronics Engineers Inc., 7577346

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

D-tdma data buses with CSMA/CD arbitration bus on wireless 3D IC

Matsumura, G., Koibuchi, M., Amano, H. & Matsutani, H., 2016, Proceedings of the 13th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2016. Acta Press, p. 242-249 8 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

From FLOPS to BYTES: Disruptive change in high-performance computing towards the post-moore era

Matsuoka, S., Amano, H., Nakajima, K., Inoue, K., Kudoh, T., Maruyama, N., Taura, K., Iwashita, T., Katagiri, T., Hanawa, T. & Endo, T., 2016 May 16, 2016 ACM International Conference on Computing Frontiers - Proceedings. Association for Computing Machinery, Inc, p. 274-281 8 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Leveraging FDSOI through body bias domain partitioning and bias search

Kühn, J. M., Amano, H., Bringmann, O. & Rosenstiel, W., 2016 Jun 5, Proceedings of the 53rd Annual Design Automation Conference, DAC 2016. Institute of Electrical and Electronics Engineers Inc., Vol. 05-09-June-2016. a79

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

MuCCRA4-BB: A fine-grained body biasing capable DRP

Kuhn, J. M., Ben Ahmed, A., Okuhara, H., Amano, H., Bringmann, O. & Rosenstiel, W., 2016 Jul 5, 19th IEEE Symposium on Low-Power and High-Speed Chips, IEEE COOL Chips 2016 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 7503676

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Power Optimization Considering the Chip Temperature of Low Power Reconfigurable Accelerator CMA-SOTB

Fujita, Y., Okuhara, H., Masuyama, K. & Amano, H., 2016 Mar 2, Proceedings - 2015 3rd International Symposium on Computing and Networking, CANDAR 2015. Institute of Electrical and Electronics Engineers Inc., p. 21-29 9 p. 7424265

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Randomizing Packet Memory Networks for Low-Latency Processor-Memory Communication

Fujiki, D., Matsutani, H., Koibuchi, M. & Amano, H., 2016 Mar 31, Proceedings - 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2016. Institute of Electrical and Electronics Engineers Inc., p. 168-175 8 p. 7445327

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Trax solver on Zynq with Deep Q-Network

Sugimoto, N., Mitsuishi, T., Kaneda, T., Tsuruta, C., Sakai, R., Shimura, H. & Amano, H., 2016 Jan 25, 2015 International Conference on Field Programmable Technology, FPT 2015. Institute of Electrical and Electronics Engineers Inc., p. 272-275 4 p. 7393122

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Zynq cluster for CFD parametric survey

Sugimoto, N., Miyajima, T., Sakai, R., Osana, Y., Fujita, N. & Amano, H., 2016, Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Springer Verlag, Vol. 9625. p. 287-299 13 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 9625).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2015

3D Shared Bus Architecture Using Inductive Coupling Interconnect

Nomura, A., Fujita, Y., Matsutani, H. & Amano, H., 2015 Nov 11, Proceedings - IEEE 9th International Symposium on Embedded Multicore/Manycore SoCs, MCSoC 2015. Institute of Electrical and Electronics Engineers Inc., p. 259-266 8 p. 7328213

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7MOPS/lemon-battery image processing demonstration with an ultra-low power reconfigurable accelerator CMA-SOTB-2

Masuyama, K., Fujita, Y., Okuhara, H. & Amano, H., 2015 Oct 7, 25th International Conference on Field Programmable Logic and Applications, FPL 2015. Institute of Electrical and Electronics Engineers Inc., 7293964

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

A leakage current monitor circuit using silicon on thin BOX MOSFET for dynamic back gate bias control

Okuhara, H., Usami, K. & Amano, H., 2015 Jul 14, IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips XVIII - Proceedings. Institute of Electrical and Electronics Engineers Inc., 7158656

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A metamorphotic Network-on-Chip for various types of parallel applications

Tade, S., Matsutani, H., Amano, H. & Koibuchi, M., 2015 Sep 8, Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors. Institute of Electrical and Electronics Engineers Inc., Vol. 2015-September. p. 98-105 8 p. 7245715

Research output: Chapter in Book/Report/Conference proceedingConference contribution

An optimal power supply and body bias voltage for a ultra low power micro-controller with silicon on thin box MOSFET

Okuhara, H., Kitamori, K., Fujita, Y., Usami, K. & Amano, H., 2015 Sep 21, Proceedings of the International Symposium on Low Power Electronics and Design. Institute of Electrical and Electronics Engineers Inc., Vol. 2015-September. p. 207-212 6 p. 7273515

Research output: Chapter in Book/Report/Conference proceedingConference contribution

13 Citations (Scopus)

A preliminarily evaluation of PEACH3: A switching hub for tightly coupled accelerators

Kuhara, T., Kaneda, T., Hanawa, T., Kodama, Y., Boku, T. & Amano, H., 2015 Feb 27, Proceedings - 2014 2nd International Symposium on Computing and Networking, CANDAR 2014. Institute of Electrical and Electronics Engineers Inc., p. 377-381 5 p. 7052213

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Design of a low power NoC router using marching memory through type

Yasudo, R., Kagami, T., Amano, H., Nakase, Y., Watanabe, M., Oishi, T., Shimizu, T. & Nakamura, T., 2015 Jan 13, Proceedings - 2014 8th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2014. Institute of Electrical and Electronics Engineers Inc., p. 111-118 8 p. 7008769

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Expandable Chip Stacking Method for Many-core Architectures Consisting of Tiny Chips

Nakahara, H., Ozaki, T., Matsutani, H., Koibuchi, M. & Amano, H., 2015 Nov 11, Proceedings - IEEE 9th International Symposium on Embedded Multicore/Manycore SoCs, MCSoC 2015. Institute of Electrical and Electronics Engineers Inc., p. 41-48 8 p. 7328185

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Fined-grained body biasing for frequency scaling in advanced SOI processes

Kuhn, J. M., Amano, H., Bringmann, O. & Rosenstiel, W., 2015 Jul 14, IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips XVIII - Proceedings. Institute of Electrical and Electronics Engineers Inc., 7158655

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

FPGA implementation of viscous function in a package for computational fluid dynamics

Mishra, D., Hatto, M., Kuhara, T., Fujita, N., Osana, Y. & Amano, H., 2015 Feb 27, Proceedings - 2014 2nd International Symposium on Computing and Networking, CANDAR 2014. Institute of Electrical and Electronics Engineers Inc., p. 608-610 3 p. 7052258

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Image processing by A 0.3V 2MW coarse-grained reconfigurable accelerator CMA-SOTB with a solar battery

Fujita, Y., Masuyama, K. & Amano, H., 2015 Apr 8, Proceedings of the 2014 International Conference on Field-Programmable Technology, FPT 2014. Institute of Electrical and Electronics Engineers Inc., p. 354-357 4 p. 7082818

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

On-chip decentralized routers with balanced pipelines for avoiding interconnect bottleneck

Yasudo, R., Matsutani, H., Koibuchi, M., Amano, H. & Nakamura, T., 2015 Sep 28, Proceedings - 2015 9th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2015. Association for Computing Machinery, Inc, 2817280

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Optimized core-links for low-latency NoCs

Kawano, R., Tade, S., Fujiwara, I., Matsutani, H., Amano, H. & Koibuchi, M., 2015, Proceedings - 23rd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2015. Institute of Electrical and Electronics Engineers Inc., p. 172-176 5 p. 7092716

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Reduction calculator in an FPGA based switching Hub for high performance clusters

Kuhara, T., Tsuruta, C., Hanawa, T. & Amano, H., 2015 Oct 7, 25th International Conference on Field Programmable Logic and Applications, FPL 2015. Institute of Electrical and Electronics Engineers Inc., 7293985

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)