• 2520 Citations
  • 23 h-Index
1983 …2020

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2012

Removing context memory from a multi-context dynamically reconfigurable processor

Amano, H., Kimura, M. & Ozaki, N., 2012, Proceedings - IEEE 6th International Symposium on Embedded Multicore SoCs, MCSoC 2012. p. 92-99 8 p. 6354683

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Trade-off analysis of fine-grained power gating methods for functional units in a CPU

Wang, W., Ohta, Y., Ishii, Y., Usami, K. & Amano, H., 2012, Symposium on Low-Power and High-Speed Chips - Proceedings for 2012 IEEE COOL Chips XV. 6216587

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Vertical link on/off control methods for wireless 3-D NoCs

Zhang, H., Matsutani, H., Take, Y., Kuroda, T. & Amano, H., 2012, Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Vol. 7179 LNCS. p. 212-224 13 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 7179 LNCS).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)
2011

A 2.72GOPS/11mW low power reconfigurable accelerator with a highly parallel datapath consisting of combinatorial circuits in 65nm CMOS

Ozaki, N., Yasuda, Y., Saito, Y., Ikebuchi, D., Kimura, M., Amano, H., Nakamura, H., Usami, K., Namiki, M. & Kondo, M., 2011, 2011 International Symposium on Integrated Circuits, ISIC 2011. p. 579-584 6 p. 6131929

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A design of one-dimensional Euler equations for fluid dynamics on FPGA

Abu Talip, M. S. & Amano, H., 2011, Proceedings of 2011 1st International Symposium on Access Spaces, ISAS 2011. p. 170-173 4 p. 5960942

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

A dynamic link-width optimization for network-on-chip

Wang, D., Koibuchi, M., Yoneda, T., Matsutani, H. & Amano, H., 2011, Proceedings - 1st International Workshop on Cyber-Physical Systems, Networks, and Applications, CPSNA 2011, Workshop Held During RTCSA 2011. Vol. 2. p. 106-108 3 p. 602900

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

A vertical bubble flow network using inductive-coupling for 3-D CMPs

Matsutani, H., Take, Y., Sasaki, D., Kimura, M., Ono, Y., Nishiyama, Y., Koibuchi, M., Kuroda, T. & Amano, H., 2011, NOCS 2011: The 5th ACM/IEEE International Symposium on Networks-on-Chip. p. 49-56 8 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

17 Citations (Scopus)

Cool mega-array: A highly energy efficient reconfigurable accelerator

Ozaki, N., Yoshihiro, Y., Saito, Y., Ikebuchi, D., Kimura, M., Amano, H., Nakamura, H., Usami, K., Namiki, M. & Kondo, M., 2011, 2011 International Conference on Field-Programmable Technology, FPT 2011. 6132668

Research output: Chapter in Book/Report/Conference proceedingConference contribution

13 Citations (Scopus)

Dynamic VDD switching technique and mapping optimization in dynamically reconfigurable processor for efficient energy reduction

Yamamoto, T., Hironaka, K., Hayakawa, Y., Kimura, M., Amano, H. & Usami, K., 2011, Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Vol. 6578 LNCS. p. 230-241 12 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 6578 LNCS).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Citations (Scopus)

Geyser-2: The second prototype CPU with fine-grained run-time power gating

Zhao, L., Ikebuchi, D., Saito, Y., Kamata, M., Seki, N., Kojima, Y., Amano, H., Koyama, S., Hashida, T., Umahashi, Y., Masuda, D., Usami, K., Kimura, K., Namiki, M., Takeda, S., Nakamura, H. & Kondo, M., 2011, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. p. 87-88 2 p. 5722310

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Citations (Scopus)

On-chip detection methodology for break-even time of power gated function units

Usami, K., Goto, Y., Matsunaga, K., Koyama, S., Ikebuchi, D., Amano, H. & Nakamura, H., 2011, Proceedings of the International Symposium on Low Power Electronics and Design. p. 241-246 6 p. 5993643

Research output: Chapter in Book/Report/Conference proceedingConference contribution

13 Citations (Scopus)

Performance evaluation of multiple lookup tables algorithms for generating CRC on an FPGA

Akagić, A. & Amano, H., 2011, Proceedings of 2011 1st International Symposium on Access Spaces, ISAS 2011. p. 164-169 6 p. 5960941

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Performance evaluation of power-aware multi-tree ethernet for HPC interconnects

Koibuchi, M., Watanabe, T., Minamihata, A., Nakao, M., Hiroyasu, T., Matsutani, H. & Amano, H., 2011, Proceedings - 2011 2nd International Conference on Networking and Computing, ICNC 2011. p. 50-57 8 p. 6131793

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Power centric application mapping for dynamically reconfigurable processor array with Dual Vdd and Dual Vth

Hironaka, K. & Amano, H., 2011, Proceedings - 2011 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2011. p. 404-409 6 p. 6128611

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Proposal of auto MPI expansion tool for cell broadband engine cluster

Nakahama, T., Yamada, M., Yoshimi, M. & Amano, H., 2011, Proceedings - 2011 2nd International Conference on Networking and Computing, ICNC 2011. p. 166-172 7 p. 6131802

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Reducing power for dynamically reconfigurable processor array by reducing number of reconfigurations

Kimura, M., Hironaka, K. & Amano, H., 2011, 2011 International Conference on Field-Programmable Technology, FPT 2011. 6132707

Research output: Chapter in Book/Report/Conference proceedingConference contribution

SLD-1(Silent Large Datapath): A ultra low power reconfigurable accelerator

Ozaki, N., Usami, K., Amano, H., Namiki, M., Nakamura, H. & Kondo, M., 2011, IEEE Symposium on Low-Power and High-Speed Chips - 2011 IEEE COOL Chips XIV, Proceedings. 5890918

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

The realtime image processing demonstration with CMA-1: An ultra low-power reconfigurable accelerator

Hironaka, K., Ozaki, N. & Amano, H., 2011, 2011 International Conference on Field-Programmable Technology, FPT 2011. 6132686

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Time and space-multiplexed compilation challenges for dynamically reconfigurable processors

Toi, T., Awashima, T., Motomura, M. & Amano, H., 2011, Midwest Symposium on Circuits and Systems. 6026300

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Vegeta: An implementation and evaluation of development-support middleware on multiple OpenCL platform

Shitara, A., Nakahama, T., Yamada, M., Kamata, T., Nishikawa, Y., Yoshimi, M. & Amano, H., 2011, Proceedings - 2011 2nd International Conference on Networking and Computing, ICNC 2011. p. 141-147 7 p. 6131828

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)
2010

Adaptive power gating for function units in a microprocessor

Usami, K., Hashida, T., Koyama, S., Yamamoto, T., Ikebuchi, D., Amano, H., Namiki, M., Kondo, M. & Nakamura, H., 2010, Proceedings of the 11th International Symposium on Quality Electronic Design, ISQED 2010. p. 29-37 9 p. 5450407

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

A datapath classification method for FPGA-based scientific application accelerator systems

Ogawa, Y., Ooya, T., Osana, Y., Yoshimi, M., Nishikawa, Y., Funahashi, A., Hiroi, N., Amano, H., Shibata, Y. & Oguri, K., 2010, Proceedings - 2010 International Conference on Field-Programmable Technology, FPT'10. p. 441-444 4 p. 5681455

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A deadlock-free non-minimal fully adaptive routing using virtual cut-through switching

Nishikawa, Y., Koibuchi, M., Matsutani, H. & Amano, H., 2010, Proceedings - 2010 IEEE International Conference on Networking, Architecture and Storage, NAS 2010. p. 431-438 8 p. 5575700

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A low-power fault-tolerant noc using error correction and detection codes

Kojima, Y., Matsutani, H., Koibuchi, M. & Amano, H., 2010, Proceedings of the 9th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2010. p. 111-118 8 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A performance evaluation of CUBE: One-dimensional 512 FPGA cluster

Yoshimi, M., Nishikawa, Y., Miki, M., Hiroyasu, T., Amano, H. & Mencer, O., 2010, Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Vol. 5992 LNCS. p. 372-381 10 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 5992 LNCS).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

A proposal of thread virtualization environment for cell broadband engine

Yamada, M., Nishikawa, Y., Yoshimi, M. & Amano, H., 2010, Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Systems. p. 32-39 8 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

A variable-pipeline on-chip router optimized to traffic pattern

Hirata, Y., Matsutani, H., Koibuchi, M. & Amano, H., 2010, 3rd International Workshop on Network on Chip Architectures, NoCArc 2010, in Conjunction with the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-43. p. 57-62 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Geyser-1: A MIPS R3000 CPU core with fine-grained run-time power gating

Ikebuchi, D., Seki, N., Kojima, Y., Kamata, M., Zhao, L., Amano, H., Shirai, T., Koyama, S., Hashida, T., Umahashi, Y., Masuda, H., Usami, K., Takeda, S., Nakamura, H., Namiki, M. & Kondo, M., 2010, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. p. 369-370 2 p. 5419857

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

MuCCRA-3: A low power dynamically reconfigurable processor array

Saito, Y., Sano, T., Kato, M., Tunbunheng, V., Yasuda, Y., Kimura, M. & Amano, H., 2010, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. p. 377-378 2 p. 5419853

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Performance, cost, and power evaluations of on-chip network topologies in FPGAs

In, S., Matsutani, H., Koibuchi, M., Wang, D. & Amano, H., 2010, Proceedings of the 9th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2010. p. 181-189 9 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Preliminary evaluation of batch-learning self-organizing map algorithm on a graphic processor

Shitara, A., Nishikawa, Y., Yoshimi, M., Abe, T., Ikemura, T. & Amano, H., 2010, Proceedings of the 9th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2010. p. 96-104 9 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Reducing instruction TLB's leakage power consumption for embedded processors

Lei, Z., Xu, H., Ikebuchi, D., Amano, H., Sunata, T. & Namiki, M., 2010, 2010 International Conference on Green Computing, Green Comp 2010. p. 477-484 8 p. 5598277

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Reducing power consumption for dynamically reconfigurable processor array with partially fixed configuration mapping

Hironaka, K., Kimura, M., Saito, Y., Sano, T., Kato, M., Tunbunheng, V., Yasuda, Y. & Amano, H., 2010, Proceedings - 2010 International Conference on Field-Programmable Technology, FPT'10. p. 349-352 4 p. 5681431

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Stabilizing Path Modification of Power-Aware On/Off Interconnection Networks

Montañana, J. M., Koibuchi, M., Matsutani, H. & Amano, H., 2010, Proceedings - 2010 IEEE International Conference on Networking, Architecture and Storage, NAS 2010. p. 218-227 10 p. 5575649

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Ultra fine-grained run-time power gating of on-chip routers for CMPs

Matsutani, H., Koibuchi, M., Ikebuchi, D., Usami, K., Nakamura, H. & Amano, H., 2010, NOCS 2010 - The 4th ACM/IEEE International Symposium on Networks-on-Chip. p. 61-68 8 p. 5507560

Research output: Chapter in Book/Report/Conference proceedingConference contribution

45 Citations (Scopus)

Wire congestion aware synthesis for a dynamically reconfigurable processor

Toi, T., Okamoto, T., Awashima, T., Wakabayashi, K. & Amano, H., 2010, Proceedings - 2010 International Conference on Field-Programmable Technology, FPT'10. p. 300-303 4 p. 5681481

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)
2009

A modular approach to heterogeneous biochemical model simulation on an FPGA

Yamada, H., Osana, Y., Ishimori, T., Ooya, T., Yoshimi, M., Nishikawa, Y., Funahashi, A., Hiroi, N., Amano, H., Shibata, Y. & Oguri, K., 2009, ReConFig'09 - 2009 International Conference on ReConFigurable Computing and FPGAs. p. 125-130 6 p. 5382039

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

An on/off link activation method for low-power ethernet in PC clusters

Koibuchi, M., Otsuka, T., Matsutani, H. & Amano, H., 2009, IPDPS 2009 - Proceedings of the 2009 IEEE International Parallel and Distributed Processing Symposium. 5161069

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Citations (Scopus)

A scalable 3D processor by homogeneous chip stacking with inductive-coupling link

Kohama, Y., Sugimori, Y., Saito, S., Hasegawa, Y., Sano, T., Kasuga, K., Yoshida, Y., Niitsu, K., Miura, N., Amano, H. & Kuroda, T., 2009, IEEE Symposium on VLSI Circuits, Digest of Technical Papers. p. 94-95 2 p. 5205288

Research output: Chapter in Book/Report/Conference proceedingConference contribution

15 Citations (Scopus)

A study on interconnection networks of the dynamically reconfigurable processor array MuCCRA

Kato, M., Sano, T., Yasuda, Y., Saito, Y. & Amano, H., 2009, Proceedings of the 2009 International Conference on Field-Programmable Technology, FPT'09. p. 415-418 4 p. 5377694

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Balanced dimension-order routing for k-ary n-cubes

Montañana, J. M., Koibuchi, M., Matsutani, H. & Amano, H., 2009, Proceedings of the International Conference on Parallel Processing Workshops. p. 499-506 8 p. 5365405

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Configuring area and performance: Empirical evaluation on an FPGA-based biochemical simulator

Ooya, T., Yamada, H., Ishimori, T., Shibata, Y., Osana, Y., Oguri, K., Yoshimi, M., Nishikawa, Y., Funahashi, A., Hiroi, N. & Amano, H., 2009, FPL 09: 19th International Conference on Field Programmable Logic and Applications. p. 679-682 4 p. 5272335

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Design and implementation of fine-grain power gating with ground bounce suppression

Usami, K., Shirai, T., Hashida, T., Masuda, H., Takeda, S., Nakata, M., Seki, N., Amano, H., Namiki, M., Imai, M., Kondo, M. & Nakamura, H., 2009, Proceedings: 22nd International Conference on VLSI Design - Held Jointly with 7th International Conference on Embedded Systems. p. 381-386 6 p. 4749703

Research output: Chapter in Book/Report/Conference proceedingConference contribution

25 Citations (Scopus)

Embedded software compression with split echo instructions

Stubdal, I., Karaduman, A. & Amano, H., 2009, Digest of Technical Papers - IEEE International Conference on Consumer Electronics. p. 816-818 3 p. 5157058

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Evaluation of a multicore reconfigurable architecture with variable core sizes

Tuan, V. M., Katsura, N., Matsutani, H. & Amano, H., 2009, IPDPS 2009 - Proceedings of the 2009 IEEE International Parallel and Distributed Processing Symposium. 5161225

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Fine grain partial reconfiguration for energy saving in dynamically reconfigurable processors

Sano, T., Saito, Y., Kato, M. & Amano, H., 2009, FPL 09: 19th International Conference on Field Programmable Logic and Applications. p. 530-533 4 p. 5272435

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Geyser-1: A MIPS R3000 CPU core with fine grain runtime power gating

Ikebuchi, D., Seki, N., Kojima, Y., Kamata, M., Zhao, L., Amano, H., Shirai, T., Koyamat, S., Hashida, T., Umahashi, Y., Masuda, H., Usami, K., Takeda, S., Nakamura, H., Namiki, M. & Kondo, M., 2009, Proceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009. p. 281-284 4 p. 5357257

Research output: Chapter in Book/Report/Conference proceedingConference contribution

33 Citations (Scopus)

Implementation and evaluation of fine-grain run-time power gating for a multiplier

Usami, K., Nakata, M., Shirai, T., Takeda, S., Seki, N., Amano, H. & Nakamura, H., 2009, 2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009. p. 7-10 4 p. 5166253

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Implementation and evaluation of self-organizing map algorithm on a graphic processor

Shitara, A., Nishikawa, Y., Yoshimi, M. & Amano, H., 2009, Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Systems. p. 253-260 8 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Leakage power reduction for coarse-grained dynamically reconfigurable processor arrays using dual Vt cells

Hirai, K., Kato, M., Saito, Y. & Amano, H., 2009, Proceedings of the 2009 International Conference on Field-Programmable Technology, FPT'09. p. 104-111 8 p. 5377641

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)