• Source: Scopus
  • Calculated based on no. of publications stored in Pure and citations from Scopus
1983 …2021

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  • 2012

    Cost effective implementation of flux limiter functions using partial reconfiguration

    Abu Talip, M. S., Akamine, T., Osana, Y., Fujita, N. & Amano, H., 2012, Reconfigurable Computing: Architectures, Tools and Applications - 8th International Symposium, ARC 2012, Proceedings. p. 215-226 12 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 7199 LNCS).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    1 Citation (Scopus)
  • Dynamically reconfigurable flux limiter functions in MUSCL scheme

    Talip, M. S. A., Akamine, T., Osana, Y., Fujita, N. & Amano, H., 2012 Nov 23, ReCoSoC 2012 - 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip, Proceedings. 6322878. (ReCoSoC 2012 - 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip, Proceedings).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • Dynamic power control with a heterogeneous multi-core system using a 3-D wireless inductive coupling interconnect

    Koizumi, Y., Amano, H., Matsutani, H., Miura, N., Kuroda, T., Sakamoto, R., Namiki, M., Usami, K., Kondo, M. & Nakamura, H., 2012 Dec 1, FPT 2012 - 2012 International Conference on Field-Programmable Technology. p. 293-296 4 p. 6412150. (FPT 2012 - 2012 International Conference on Field-Programmable Technology).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    7 Citations (Scopus)
  • Extension of memory controller equipped with MuCCRA-3-DP: Dynamically reconfigurable processor array

    Katagiri, T., Hironaka, K. & Amano, H., 2012 Dec 14, Proceedings of the 2012 15th International Conference on Network-Based Information Systems, NBIS 2012. p. 826-831 6 p. 6354932. (Proceedings of the 2012 15th International Conference on Network-Based Information Systems, NBIS 2012).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    2 Citations (Scopus)
  • Performance analysis of fully-adaptable CRC accelerators on an FPGA

    Akagic, A. & Amano, H., 2012 Dec 12, Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012. p. 575-578 4 p. 6339374. (Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • Reconfigurable out-of-order mechanism generator for unstructured grid computation in computational fluid dynamics

    Akamine, T., Inakagata, K., Osana, Y., Fujita, N. & Amano, H., 2012 Dec 12, Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012. p. 136-142 7 p. 6339277. (Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    5 Citations (Scopus)
  • Trade-off analysis of fine-grained power gating methods for functional units in a CPU

    Wang, W., Ohta, Y., Ishii, Y., Usami, K. & Amano, H., 2012 Jul 25, Symposium on Low-Power and High-Speed Chips - Proceedings for 2012 IEEE COOL Chips XV. 6216587. (Symposium on Low-Power and High-Speed Chips - Proceedings for 2012 IEEE COOL Chips XV).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    4 Citations (Scopus)
  • Vertical link on/off control methods for wireless 3-D NoCs

    Zhang, H., Matsutani, H., Take, Y., Kuroda, T. & Amano, H., 2012 Feb 28, Architecture of Computing Systems, ARCS 2012 - 25th International Conference, Proceedings. p. 212-224 13 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 7179 LNCS).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    1 Citation (Scopus)
  • 2011

    A 2.72GOPS/11mW low power reconfigurable accelerator with a highly parallel datapath consisting of combinatorial circuits in 65nm CMOS

    Ozaki, N., Yasuda, Y., Saito, Y., Ikebuchi, D., Kimura, M., Amano, H., Nakamura, H., Usami, K., Namiki, M. & Kondo, M., 2011, 2011 International Symposium on Integrated Circuits, ISIC 2011. p. 579-584 6 p. 6131929. (2011 International Symposium on Integrated Circuits, ISIC 2011).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • A design of one-dimensional Euler equations for fluid dynamics on FPGA

    Abu Talip, M. S. & Amano, H., 2011, Proceedings of 2011 1st International Symposium on Access Spaces, ISAS 2011. p. 170-173 4 p. 5960942. (Proceedings of 2011 1st International Symposium on Access Spaces, ISAS 2011).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    1 Citation (Scopus)
  • A dynamic link-width optimization for network-on-chip

    Wang, D., Koibuchi, M., Yoneda, T., Matsutani, H. & Amano, H., 2011 Dec 1, Proceedings - 1st International Workshop on Cyber-Physical Systems, Networks, and Applications, CPSNA 2011, Workshop Held During RTCSA 2011. p. 106-108 3 p. 602900. (Proceedings - 1st International Workshop on Cyber-Physical Systems, Networks, and Applications, CPSNA 2011, Workshop Held During RTCSA 2011; vol. 2).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    1 Citation (Scopus)
  • A vertical bubble flow network using inductive-coupling for 3-D CMPs

    Matsutani, H., Take, Y., Sasaki, D., Kimura, M., Ono, Y., Nishiyama, Y., Koibuchi, M., Kuroda, T. & Amano, H., 2011, NOCS 2011: The 5th ACM/IEEE International Symposium on Networks-on-Chip. p. 49-56 8 p. (NOCS 2011: The 5th ACM/IEEE International Symposium on Networks-on-Chip).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    17 Citations (Scopus)
  • Cool mega-array: A highly energy efficient reconfigurable accelerator

    Ozaki, N., Yoshihiro, Y., Saito, Y., Ikebuchi, D., Kimura, M., Amano, H., Nakamura, H., Usami, K., Namiki, M. & Kondo, M., 2011, 2011 International Conference on Field-Programmable Technology, FPT 2011. 6132668. (2011 International Conference on Field-Programmable Technology, FPT 2011).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    15 Citations (Scopus)
  • Dynamic VDD switching technique and mapping optimization in dynamically reconfigurable processor for efficient energy reduction

    Yamamoto, T., Hironaka, K., Hayakawa, Y., Kimura, M., Amano, H. & Usami, K., 2011, Reconfigurable Computing: Architectures, Tools and Applications - 7th International Symposium, ARC 2011, Proceedings. p. 230-241 12 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 6578 LNCS).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    9 Citations (Scopus)
  • Geyser-2: The second prototype CPU with fine-grained run-time power gating

    Zhao, L., Ikebuchi, D., Saito, Y., Kamata, M., Seki, N., Kojima, Y., Amano, H., Koyama, S., Hashida, T., Umahashi, Y., Masuda, D., Usami, K., Kimura, K., Namiki, M., Takeda, S., Nakamura, H. & Kondo, M., 2011 Mar 28, 2011 16th Asia and South Pacific Design Automation Conference, ASP-DAC 2011. p. 87-88 2 p. 5722310. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    11 Citations (Scopus)
  • On-chip detection methodology for break-even time of power gated function units

    Usami, K., Goto, Y., Matsunaga, K., Koyama, S., Ikebuchi, D., Amano, H. & Nakamura, H., 2011 Sep 19, IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011. p. 241-246 6 p. 5993643. (Proceedings of the International Symposium on Low Power Electronics and Design).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    14 Citations (Scopus)
  • Performance evaluation of multiple lookup tables algorithms for generating CRC on an FPGA

    Akagić, A. & Amano, H., 2011 Aug 23, Proceedings of 2011 1st International Symposium on Access Spaces, ISAS 2011. p. 164-169 6 p. 5960941. (Proceedings of 2011 1st International Symposium on Access Spaces, ISAS 2011).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    4 Citations (Scopus)
  • Performance evaluation of power-aware multi-tree ethernet for HPC interconnects

    Koibuchi, M., Watanabe, T., Minamihata, A., Nakao, M., Hiroyasu, T., Matsutani, H. & Amano, H., 2011, Proceedings - 2011 2nd International Conference on Networking and Computing, ICNC 2011. p. 50-57 8 p. 6131793. (Proceedings - 2011 2nd International Conference on Networking and Computing, ICNC 2011).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • Power centric application mapping for dynamically reconfigurable processor array with Dual Vdd and Dual Vth

    Hironaka, K. & Amano, H., 2011 Dec 1, Proceedings - 2011 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2011. p. 404-409 6 p. 6128611. (Proceedings - 2011 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2011).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    2 Citations (Scopus)
  • Proposal of auto MPI expansion tool for cell broadband engine cluster

    Nakahama, T., Yamada, M., Yoshimi, M. & Amano, H., 2011, Proceedings - 2011 2nd International Conference on Networking and Computing, ICNC 2011. p. 166-172 7 p. 6131802. (Proceedings - 2011 2nd International Conference on Networking and Computing, ICNC 2011).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • Reducing power for dynamically reconfigurable processor array by reducing number of reconfigurations

    Kimura, M., Hironaka, K. & Amano, H., 2011 Dec 1, 2011 International Conference on Field-Programmable Technology, FPT 2011. 6132707. (2011 International Conference on Field-Programmable Technology, FPT 2011).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • SLD-1(Silent Large Datapath): A ultra low power reconfigurable accelerator

    Ozaki, N., Usami, K., Amano, H., Namiki, M., Nakamura, H. & Kondo, M., 2011, IEEE Symposium on Low-Power and High-Speed Chips - 2011 IEEE COOL Chips XIV, Proceedings. 5890918. (IEEE Symposium on Low-Power and High-Speed Chips - 2011 IEEE COOL Chips XIV, Proceedings).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    2 Citations (Scopus)
  • The realtime image processing demonstration with CMA-1: An ultra low-power reconfigurable accelerator

    Hironaka, K., Ozaki, N. & Amano, H., 2011 Dec 1, 2011 International Conference on Field-Programmable Technology, FPT 2011. 6132686. (2011 International Conference on Field-Programmable Technology, FPT 2011).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • Time and space-multiplexed compilation challenges for dynamically reconfigurable processors

    Toi, T., Awashima, T., Motomura, M. & Amano, H., 2011 Oct 13, 54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011. 6026300. (Midwest Symposium on Circuits and Systems).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    2 Citations (Scopus)
  • Vegeta: An implementation and evaluation of development-support middleware on multiple OpenCL platform

    Shitara, A., Nakahama, T., Yamada, M., Kamata, T., Nishikawa, Y., Yoshimi, M. & Amano, H., 2011, Proceedings - 2011 2nd International Conference on Networking and Computing, ICNC 2011. p. 141-147 7 p. 6131828. (Proceedings - 2011 2nd International Conference on Networking and Computing, ICNC 2011).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    3 Citations (Scopus)
  • 2010

    Adaptive power gating for function units in a microprocessor

    Usami, K., Hashida, T., Koyama, S., Yamamoto, T., Ikebuchi, D., Amano, H., Namiki, M., Kondo, M. & Nakamura, H., 2010 May 28, Proceedings of the 11th International Symposium on Quality Electronic Design, ISQED 2010. p. 29-37 9 p. 5450407. (Proceedings of the 11th International Symposium on Quality Electronic Design, ISQED 2010).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    7 Citations (Scopus)
  • A datapath classification method for FPGA-based scientific application accelerator systems

    Ogawa, Y., Ooya, T., Osana, Y., Yoshimi, M., Nishikawa, Y., Funahashi, A., Hiroi, N., Amano, H., Shibata, Y. & Oguri, K., 2010, Proceedings - 2010 International Conference on Field-Programmable Technology, FPT'10. p. 441-444 4 p. 5681455. (Proceedings - 2010 International Conference on Field-Programmable Technology, FPT'10).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • A deadlock-free non-minimal fully adaptive routing using virtual cut-through switching

    Nishikawa, Y., Koibuchi, M., Matsutani, H. & Amano, H., 2010 Oct 27, Proceedings - 2010 IEEE International Conference on Networking, Architecture and Storage, NAS 2010. p. 431-438 8 p. 5575700. (Proceedings - 2010 IEEE International Conference on Networking, Architecture and Storage, NAS 2010).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • A low-power fault-tolerant noc using error correction and detection codes

    Kojima, Y., Matsutani, H., Koibuchi, M. & Amano, H., 2010 Jan 1, Proceedings of the 9th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2010. Acta Press, p. 111-118 8 p. (Proceedings of the 9th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2010).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • A performance evaluation of CUBE: One-dimensional 512 FPGA cluster

    Yoshimi, M., Nishikawa, Y., Miki, M., Hiroyasu, T., Amano, H. & Mencer, O., 2010 Apr 29, Reconfigurable Computing: Architectures, Tools and Applications - 6th International Symposium, ARC 2010, Proceedings. p. 372-381 10 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 5992 LNCS).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    6 Citations (Scopus)
  • A proposal of thread virtualization environment for cell broadband engine

    Yamada, M., Nishikawa, Y., Yoshimi, M. & Amano, H., 2010 Dec 1, Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Systems, PDCS 2010. p. 32-39 8 p. (Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Systems).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    2 Citations (Scopus)
  • A variable-pipeline on-chip router optimized to traffic pattern

    Hirata, Y., Matsutani, H., Koibuchi, M. & Amano, H., 2010, 3rd International Workshop on Network on Chip Architectures, NoCArc 2010, in Conjunction with the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-43. p. 57-62 6 p. (3rd International Workshop on Network on Chip Architectures, NoCArc 2010, in Conjunction with the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-43).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    7 Citations (Scopus)
  • Geyser-1: A MIPS R3000 CPU core with fine-grained run-time power gating

    Ikebuchi, D., Seki, N., Kojima, Y., Kamata, M., Zhao, L., Amano, H., Shirai, T., Koyama, S., Hashida, T., Umahashi, Y., Masuda, H., Usami, K., Takeda, S., Nakamura, H., Namiki, M. & Kondo, M., 2010, 2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010. p. 369-370 2 p. 5419857. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    4 Citations (Scopus)
  • MuCCRA-3: A low power dynamically reconfigurable processor array

    Saito, Y., Sano, T., Kato, M., Tunbunheng, V., Yasuda, Y., Kimura, M. & Amano, H., 2010, 2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010. p. 377-378 2 p. 5419853. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    5 Citations (Scopus)
  • Performance, cost, and power evaluations of on-chip network topologies in FPGAs

    In, S., Matsutani, H., Koibuchi, M., Wang, D. & Amano, H., 2010 Jul 20, Proceedings of the 9th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2010. p. 181-189 9 p. (Proceedings of the 9th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2010).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • Preliminary evaluation of batch-learning self-organizing map algorithm on a graphic processor

    Shitara, A., Nishikawa, Y., Yoshimi, M., Abe, T., Ikemura, T. & Amano, H., 2010, Proceedings of the 9th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2010. Acta Press, p. 96-104 9 p. (Proceedings of the 9th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2010).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • Reducing instruction TLB's leakage power consumption for embedded processors

    Lei, Z., Xu, H., Ikebuchi, D., Amano, H., Sunata, T. & Namiki, M., 2010, 2010 International Conference on Green Computing, Green Comp 2010. IEEE Computer Society, p. 477-484 8 p. 5598277. (2010 International Conference on Green Computing, Green Comp 2010).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    2 Citations (Scopus)
  • Reducing power consumption for dynamically reconfigurable processor array with partially fixed configuration mapping

    Hironaka, K., Kimura, M., Saito, Y., Sano, T., Kato, M., Tunbunheng, V., Yasuda, Y. & Amano, H., 2010 Dec 1, Proceedings - 2010 International Conference on Field-Programmable Technology, FPT'10. p. 349-352 4 p. 5681431. (Proceedings - 2010 International Conference on Field-Programmable Technology, FPT'10).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    1 Citation (Scopus)
  • Stabilizing Path Modification of Power-Aware On/Off Interconnection Networks

    Montañana, J. M., Koibuchi, M., Matsutani, H. & Amano, H., 2010 Oct 28, Proceedings - 2010 IEEE International Conference on Networking, Architecture and Storage, NAS 2010. p. 218-227 10 p. 5575649. (Proceedings - 2010 IEEE International Conference on Networking, Architecture and Storage, NAS 2010).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • Ultra fine-grained run-time power gating of on-chip routers for CMPs

    Matsutani, H., Koibuchi, M., Ikebuchi, D., Usami, K., Nakamura, H. & Amano, H., 2010, NOCS 2010 - The 4th ACM/IEEE International Symposium on Networks-on-Chip. p. 61-68 8 p. 5507560. (NOCS 2010 - The 4th ACM/IEEE International Symposium on Networks-on-Chip).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    49 Citations (Scopus)
  • Wire congestion aware synthesis for a dynamically reconfigurable processor

    Toi, T., Okamoto, T., Awashima, T., Wakabayashi, K. & Amano, H., 2010 Dec 1, Proceedings - 2010 International Conference on Field-Programmable Technology, FPT'10. p. 300-303 4 p. 5681481. (Proceedings - 2010 International Conference on Field-Programmable Technology, FPT'10).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    2 Citations (Scopus)
  • 2009

    A modular approach to heterogeneous biochemical model simulation on an FPGA

    Yamada, H., Osana, Y., Ishimori, T., Ooya, T., Yoshimi, M., Nishikawa, Y., Funahashi, A., Hiroi, N., Amano, H., Shibata, Y. & Oguri, K., 2009 Dec 1, ReConFig'09 - 2009 International Conference on ReConFigurable Computing and FPGAs. p. 125-130 6 p. 5382039. (ReConFig'09 - 2009 International Conference on ReConFigurable Computing and FPGAs).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    1 Citation (Scopus)
  • An on/off link activation method for low-power ethernet in PC clusters

    Koibuchi, M., Otsuka, T., Matsutani, H. & Amano, H., 2009, IPDPS 2009 - Proceedings of the 2009 IEEE International Parallel and Distributed Processing Symposium. 5161069. (IPDPS 2009 - Proceedings of the 2009 IEEE International Parallel and Distributed Processing Symposium).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    12 Citations (Scopus)
  • A scalable 3D processor by homogeneous chip stacking with inductive-coupling link

    Kohama, Y., Sugimori, Y., Saito, S., Hasegawa, Y., Sano, T., Kasuga, K., Yoshida, Y., Niitsu, K., Miura, N., Amano, H. & Kuroda, T., 2009 Nov 18, 2009 Symposium on VLSI Circuits. p. 94-95 2 p. 5205288. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    15 Citations (Scopus)
  • A study on interconnection networks of the dynamically reconfigurable processor array MuCCRA

    Kato, M., Sano, T., Yasuda, Y., Saito, Y. & Amano, H., 2009 Dec 1, Proceedings of the 2009 International Conference on Field-Programmable Technology, FPT'09. p. 415-418 4 p. 5377694. (Proceedings of the 2009 International Conference on Field-Programmable Technology, FPT'09).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    2 Citations (Scopus)
  • Balanced dimension-order routing for k-ary n-cubes

    Montañana, J. M., Koibuchi, M., Matsutani, H. & Amano, H., 2009 Dec 1, ICPPW 2009 - The 38th International Conference Parallel Processing Workshops. p. 499-506 8 p. 5365405. (Proceedings of the International Conference on Parallel Processing Workshops).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    10 Citations (Scopus)
  • Configuring area and performance: Empirical evaluation on an FPGA-based biochemical simulator

    Ooya, T., Yamada, H., Ishimori, T., Shibata, Y., Osana, Y., Oguri, K., Yoshimi, M., Nishikawa, Y., Funahashi, A., Hiroi, N. & Amano, H., 2009 Nov 25, FPL 09: 19th International Conference on Field Programmable Logic and Applications. p. 679-682 4 p. 5272335. (FPL 09: 19th International Conference on Field Programmable Logic and Applications).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    2 Citations (Scopus)
  • Design and implementation of fine-grain power gating with ground bounce suppression

    Usami, K., Shirai, T., Hashida, T., Masuda, H., Takeda, S., Nakata, M., Seki, N., Amano, H., Namiki, M., Imai, M., Kondo, M. & Nakamura, H., 2009 Mar 30, Proceedings: 22nd International Conference on VLSI Design - Held Jointly with 7th International Conference on Embedded Systems. p. 381-386 6 p. 4749703. (Proceedings: 22nd International Conference on VLSI Design - Held Jointly with 7th International Conference on Embedded Systems).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    26 Citations (Scopus)
  • Embedded software compression with split echo instructions

    Stubdal, I., Karaduman, A. & Amano, H., 2009 Oct 27, 2009 IEEE 13th International Symposium on Consumer Electronics, ISCE 2009. p. 816-818 3 p. 5157058. (Digest of Technical Papers - IEEE International Conference on Consumer Electronics).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    1 Citation (Scopus)
  • Evaluation of a multicore reconfigurable architecture with variable core sizes

    Tuan, V. M., Katsura, N., Matsutani, H. & Amano, H., 2009 Nov 25, IPDPS 2009 - Proceedings of the 2009 IEEE International Parallel and Distributed Processing Symposium. 5161225. (IPDPS 2009 - Proceedings of the 2009 IEEE International Parallel and Distributed Processing Symposium).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    3 Citations (Scopus)