• 2520 Citations
  • 23 h-Index
1983 …2020

Research output per year

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2009

Low power image processing using MuCCRA-3: A dynamically reconfigurable processor array

Kimura, M., Saito, Y., Sano, T., Kato, M., Tunbunheng, V., Yasuda, Y. & Amano, H., 2009, Proceedings of the 2009 International Conference on Field-Programmable Technology, FPT'09. p. 364-367 4 p. 5377614

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Modularizing flux limiter functions for a computational fluid dynamics accelerator on FPGAS

Inakagata, K., Morishita, H., Osana, Y., Fujita, N. & Amano, H., 2009, FPL 09: 19th International Conference on Field Programmable Logic and Applications. p. 654-657 4 p. 5272347

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

MuCCRA-Cube: A 3D dynamically reconfigurable processor with inductive-coupling link

Saito, S., Kohama, Y., Sugimori, Y., Hasegawa, Y., Matsutani, H., Sano, T., Kasuga, K., Yoshida, Y., Niitsu, K., Miura, N., Kuroda, T. & Amano, H., 2009, FPL 09: 19th International Conference on Field Programmable Logic and Applications. p. 6-11 6 p. 5272565

Research output: Chapter in Book/Report/Conference proceedingConference contribution

21 Citations (Scopus)

Performance analysis of clearspeed's CSX600 interconnects

Nishikawa, Y., Koibuchi, M., Yoshimi, M., Shitara, A., Miura, K. & Amano, H., 2009, Proceedings - 2009 IEEE International Symposium on Parallel and Distributed Processing with Applications, ISPA 2009. p. 203-210 8 p. 5207934

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Prediction router: Yet another low latency on-chip router architecture

Matsutani, H., Koibuchi, M., Amano, H. & Yoshinaga, T., 2009, Proceedings - International Symposium on High-Performance Computer Architecture. p. 367-378 12 p. 4798274

Research output: Chapter in Book/Report/Conference proceedingConference contribution

59 Citations (Scopus)
2008

Adding slow-silent virtual channels for low-power on-chip networks

Matsutani, H., Koibuchi, M., Wang, D. & Amano, H., 2008, Proceedings - Second IEEE International Symposium on Networks-on-Chip, NOCS 2008. p. 23-32 10 p. 4492722

Research output: Chapter in Book/Report/Conference proceedingConference contribution

33 Citations (Scopus)

A Fine-grain Dynamic Sleep Control Scheme in MIPS R3000

Seki, N., Zhao, L., Kei, J., Ikebuchi, D., Kojima, Y., Hasegawa, Y., Amano, H., Toshihiro Kashima, K., Takeda, S., Shirai, T., Nakata, M., Usami, K., Sunata, T., Kanai, J., Namiki, M., Kondo, M. & Nakamura, H., 2008, 26th IEEE International Conference on Computer Design 2008, ICCD. p. 612-617 6 p. 4751924

Research output: Chapter in Book/Report/Conference proceedingConference contribution

34 Citations (Scopus)

A lightweight fault-tolerant mechanism for network-on-chip

Koibuchi, M., Matsutani, H., Amano, H. & Pinkston, T. M., 2008, Proceedings - Second IEEE International Symposium on Networks-on-Chip, NOCS 2008. p. 13-22 10 p. 4492721

Research output: Chapter in Book/Report/Conference proceedingConference contribution

107 Citations (Scopus)

A method for capturing state data on dynamically reconfigurable processors

Tuan, V. M. & Amano, H., 2008, Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2008. p. 208-214 7 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

A preemption algorithm for a multitasking environment on dynamically reconfigurable processor

Tuan, V. M. & Amano, H., 2008, Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Vol. 4943 LNCS. p. 172-184 13 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 4943 LNCS).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Design and implementation of adaptive Viterbi decoder for using a dynamic reconfigurable processor

Kishimoto, Y., Haruyama, S. & Amano, H., 2008, Proceedings - 2008 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2008. p. 247-252 6 p. 4731802

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

ESPRIT/sim: A high speed performance-simulator for heterogeneous embedded multiprocessors

Ohmiya, Y. & Amano, H., 2008, Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Systems. p. 252-257 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Evaluation of MuCCRA-D: A dynamically reconfigurable processor with directly interconnected PEs

Kato, M., Hasegawa, Y. & Amano, H., 2008, Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2008. p. 215-221 7 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Exploiting memory hierarchy for a Computational Fluid Dynamics accelerator on FPGAs

Morishita, H., Osana, Y., Fujita, N. & Amano, H., 2008, Proceedings of the 2008 International Conference on Field-Programmable Technology, ICFPT 2008. p. 193-200 8 p. 4762383

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Citations (Scopus)

Exploring the optimal size for multicasting configuration data of dynamically Reconfigurable processors

Nakamura, T., Sano, T., Hasegawa, Y., Tsutsumi, S., Tunbunheng, V. & Amano, H., 2008, Proceedings of the 2008 International Conference on Field-Programmable Technology, ICFPT 2008. p. 137-144 8 p. 4762376

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Implementation and evaluation of the mechanisms for low latency communication on DIMMnet-2

Miyabe, Y., Kitamura, A., Hamada, Y., Miyasiro, T., Izawa, T., Tanabe, N., Nakajo, H. & Amano, H., 2008, Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Vol. 4759 LNCS. p. 211-218 8 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 4759 LNCS).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Instruction buffer mode for multi-context dynamically reconfigurable processors

Sano, T., Kato, M., Tsutsumi, S., Hasegawa, Y. & Amano, H., 2008, Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL. p. 215-220 6 p. 4629934

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Leakage power Reduction for coarse grained dynamically reconfigurable processor arrays with fine grained power Gating technique

Saito, Y., Shirai, T., Nakamura, T., Nishimura, T., Hasegawa, Y., Tsutsumi, S., Kashima, T., Nakata, M., Takeda, S., Usami, K. & Amano, H., 2008, Proceedings of the 2008 International Conference on Field-Programmable Technology, ICFPT 2008. p. 329-332 4 p. 4762410

Research output: Chapter in Book/Report/Conference proceedingConference contribution

15 Citations (Scopus)

Power reduction techniques for dynamically reconfigurable processor arrays

Nishimura, T., Hirai, K., Saito, Y., Nakamura, T., Hasegawa, Y., Tsutsusmi, S., Tunbunheng, V. & Amano, H., 2008, Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL. p. 305-310 6 p. 4629949

Research output: Chapter in Book/Report/Conference proceedingConference contribution

17 Citations (Scopus)

Practical implementation of a network-based Stochastic biochemical simulation system on an FPGA

Yoshimi, M., Nishikawa, Y., Osana, Y., Funahashi, A., Hiroi, N., Shibata, Y., Yamada, H., Kitano, H. & Amano, H., 2008, Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL. p. 663-666 4 p. 4630034

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Run-time power gating of on-chip routers using look-ahead routing

Matsutani, H., Koibuchi, M., Amano, H. & Wang, D., 2008, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. p. 55-60 6 p. 4484015

Research output: Chapter in Book/Report/Conference proceedingConference contribution

64 Citations (Scopus)

Three-dimensional layout of on-chip tree-based networks

Matsutani, H., Koibuchi, M., Hsu, D. F. & Amano, H., 2008, Proceedings of the International Symposium on Parallel Architectures, Algorithms and Networks, I-SPAN. p. 281-288 8 p. 4520228

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Citations (Scopus)
2007

A combining technique of rate law functions for a cost-effective reconfigurable biological simulator

Yamada, H., Iwanaga, N., Shibata, Y., Osana, Y., Yoshimi, M., Iwaoka, Y., Nishikawa, Y., Kojima, T., Amano, H., Funahashi, A., Hiroi, N., Hiroaki Kitano, K. & Kiyoshi Oguri, O., 2007, Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL. p. 808-811 4 p. 4380774

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

A framework for implementing a network-based stochastic biochemical simulator on an FPGA

Yoshimi, M., Nishikawa, Y., Kojima, T., Osana, Y., Funahashi, A., Hiroi, N., Shibata, Y., Yamada, H., Kitano, H. & Amano, H., 2007, ICFPT 2007 - International Conference on Field Programmable Technology. p. 193-200 8 p. 4439249

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

A high speed license plate recognition system on an FPGA

Kanamori, T., Amano, H., Arai, M., Konno, D., Nanba, T. & Ajioka, Y., 2007, Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL. p. 554-557 4 p. 4380715

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

A mapping method for multi-process execution on dynamically reconfigurable processors

Vu, M. T. & Amano, H., 2007, ICFPT 2007 - International Conference on Field Programmable Technology. p. 357-360 4 p. 4439285

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

A temporal correlation based port combination methodology for Networks-on-Chip on reconfigurable systems

Wang, D., Matsutani, H., Amano, H. & Koibuchi, M., 2007, Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL. p. 383-388 6 p. 4380676

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Design methodology and trade-offs analysis for parameterized dynamically reconfigurable processor arrays

Hasegawa, Y., Tsutsumi, S., Tanbunheng, V., Nakamura, T., Nishimura, T. & Amano, H., 2007, Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL. p. 796-799 4 p. 4380771

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

FPGA implementation of a data-driven stochastic biochemical simulator with the next reaction method

Yoshimi, M., Iwaoka, Y., Nishikawa, Y., Kojima, T., Osana, Y., Funahashi, A., Hiroi, N., Shibata, Y., Iwanaga, N., Yamada, H., Kitano, H. & Amano, H., 2007, Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL. p. 254-259 6 p. 4380656

Research output: Chapter in Book/Report/Conference proceedingConference contribution

14 Citations (Scopus)

Implementation and evaluation of a high speed license plate recognition system on an FPGA

Kanamori, T., Amano, H., Arai, M., Konno, D., Nanba, T. & Ajioka, Y., 2007, CIT 2007: 7th IEEE International Conference on Computer and Information Technology. p. 567-572 6 p. 4385143

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Citations (Scopus)

Message from the technical program co-chairs

Amano, H. & Ye, A., 2007, ICFPT 2007 - International Conference on Field Programmable Technology. 4439219

Research output: Chapter in Book/Report/Conference proceedingConference contribution

MuCCRA chips: Configurable dynamically-reconfigurable processors

Amano, H., Hasegawa, Y., Tsutsumi, S., Nakamura, T., Nishimura, T., Tanbunheng, V., Parimala, A., Sano, T. & Kato, M., 2007, 2007 IEEE Asian Solid-State Circuits Conference, A-SSCC. p. 384-387 4 p. 4425711

Research output: Chapter in Book/Report/Conference proceedingConference contribution

41 Citations (Scopus)

Overwrite configuration technique in multicast configuration scheme for dynamically reconfigurable processor arrays

Tsutsumi, S., Tunbunheng, V., Hasegawa, Y., Parimala, A., Nakamura, T., Nishimura, T. & Amano, H., 2007, ICFPT 2007 - International Conference on Field Programmable Technology. p. 273-276 4 p. 4439264

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Performance, cost, and energy evaluation of fat H-tree: A cost-efficient tree-based on-chip network

Matsutani, H., Koibuchi, M. & Amano, H., 2007, Proceedings - 21st International Parallel and Distributed Processing Symposium, IPDPS 2007; Abstracts and CD-ROM. 4227999

Research output: Chapter in Book/Report/Conference proceedingConference contribution

18 Citations (Scopus)

Performance evaluation on low-latency communication mechanism of DIMMnet-2

Kitamura, A., Miyabe, Y., Miyashiro, T., Tanabe, N., Nakajo, H. & Amano, H., 2007, Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Systems. p. 57-62 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Performance improvement methodology for ClearSpeed's CSX600

Nishikawa, Y., Koibuchi, M., Yoshimi, M., Miura, K. & Amano, H., 2007, Proceedings of the International Conference on Parallel Processing. 4343884

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Tightly-coupled multi-layer topologies for 3-D NoCs

Matsutani, H., Koibuchi, M. & Amano, H., 2007, Proceedings of the International Conference on Parallel Processing. 4343882

Research output: Chapter in Book/Report/Conference proceedingConference contribution

62 Citations (Scopus)
2006

A context dependent clock control mechanism for dynamically reconfigurable processors

Amano, H., Hasegawa, Y., Abe, S., Ishikawa, K., Tsutsumi, S., Kurotaki, S., Nakamura, T. & Nishimura, T., 2006, Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL. p. 575-580 6 p. 4101031

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

A cost-effective context memory structure for dynamically reconfigurable processors

Suzuki, M., Hasegawa, Y., Tuan, V. M., Abe, S. & Amano, H., 2006, 20th International Parallel and Distributed Processing Symposium, IPDPS 2006. Vol. 2006. 1639433

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

An adaptive Viterbi decoder on the dynamically reconfigurable processor

Abe, S., Hasegawa, Y., Toi, T., Inuo, T. & Amano, H., 2006, Proceedings - 2006 IEEE International Conference on Field Programmable Technology, FPT 2006. p. 285-288 4 p. 4042451

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

An FPGA implementation of high throughput stochastic simulator for large-scale biochemical systems

Yoshimi, M., Osana, Y., Iwaoka, Y., Nishikawa, Y., Kojima, T., Shibata, Y., Iwanaga, N., Funahashi, A., Hiroi, N., Kitano, H. & Amano, H., 2006, Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL. p. 227-232 6 p. 4100980

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

A switch-tagged VLAN routing methodology for PC clusters with Ethernet

Otsuka, T., Koibuchi, M., Kudoh, T. & Amano, H., 2006, Proceedings of the International Conference on Parallel Processing. p. 479-486 8 p. 1690652

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Citations (Scopus)

DIMMnet-2: A reconfigurable board connected into a memory slot

Miyashiro, T., Kitamura, A., Yoshimi, M., Amano, H., Nakajyo, H. & Tanabe, N., 2006, Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL. p. 825-828 4 p. 4101085

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Enforcing dimension-order routing in on-chip torus networks without virtual channels

Matsutani, H., Koibuchi, M. & Amano, H., 2006, Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Springer Verlag, Vol. 4330. p. 207-218 12 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 4330).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Hardware support for MPI in DIMMnet-2 network interface

Tanabe, N., Kitamura, A., Miyashiro, T., Miyabe, Y., Araki, T., Luo, Z., Nakajo, H. & Amano, H., 2006, Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems. p. 73-80 8 p. 4089358

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Performance/cost trade-off evaluation for the DCT implementation on the dynamically reconfigurable processor

Tuan, V. M., Hasegawa, Y., Katsura, N. & Amano, H., 2006, Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Vol. 3985 LNCS. p. 115-121 7 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 3985 LNCS).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Performance and power analysis of time-multiplexed execution on dynamically reconfigurable processor

Hasegawa, Y., Abe, S., Kurotaki, S., Tuan, V. M., Katsura, N., Nakamura, T., Nishimura, T. & Amano, H., 2006, 20th International Parallel and Distributed Processing Symposium, IPDPS 2006. Vol. 2006. 1639431

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Performance evaluation of an FPGA-based biochemical simulator ReCSiP

Osana, Y., Yoshimi, M., Iwaoka, Y., Kojima, T., Nishikawa, Y., Funahashi, A., Hiroi, N., Kitano, H., Amano, H., Shibata, Y. & Iwanaga, N., 2006, Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL. p. 845-850 6 p. 4101089

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)
2005

A framework for ODE-based multimodel biochemical simulations on an FPGA

Osana, Y., Fukushima, T., Yoshimi, M., Iwaoka, Y., Funahashi, A., Hiroi, N., Shibata, Y., Iwanaga, N., Kitano, H. & Amano, H., 2005, Proceedings - 2005 International Conference on Field Programmable Logic and Applications, FPL. Vol. 2005. p. 574-577 4 p. 1515788

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

An adaptive cryptographic accelerator for IPsec on dynamically reconfigurable processor

Hasegawa, Y., Abe, S., Matsutani, H., Amano, H., Anjo, K. & Awashima, T., 2005, Proceedings - 2005 IEEE International Conference on Field Programmable Technology. Vol. 2005. p. 163-170 8 p. 1568541

Research output: Chapter in Book/Report/Conference proceedingConference contribution

16 Citations (Scopus)