• Source: Scopus
  • Calculated based on no. of publications stored in Pure and citations from Scopus
1983 …2022

Research activity per year

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  • 2006

    A context dependent clock control mechanism for dynamically reconfigurable processors

    Amano, H., Hasegawa, Y., Abe, S., Ishikawa, K., Tsutsumi, S., Kurotaki, S., Nakamura, T. & Nishimura, T., 2006, Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL. p. 575-580 6 p. 4101031. (Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    1 Citation (Scopus)
  • A cost-effective context memory structure for dynamically reconfigurable processors

    Suzuki, M., Hasegawa, Y., Tuan, V. M., Abe, S. & Amano, H., 2006, 20th International Parallel and Distributed Processing Symposium, IPDPS 2006. IEEE Computer Society, 1639433. (20th International Parallel and Distributed Processing Symposium, IPDPS 2006; vol. 2006).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    7 Citations (Scopus)
  • An adaptive Viterbi decoder on the dynamically reconfigurable processor

    Abe, S., Hasegawa, Y., Toi, T., Inuo, T. & Amano, H., 2006, Proceedings - 2006 IEEE International Conference on Field Programmable Technology, FPT 2006. p. 285-288 4 p. 4042451. (Proceedings - 2006 IEEE International Conference on Field Programmable Technology, FPT 2006).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    3 Citations (Scopus)
  • An FPGA implementation of high throughput stochastic simulator for large-scale biochemical systems

    Yoshimi, M., Osana, Y., Iwaoka, Y., Nishikawa, Y., Kojima, T., Shibata, Y., Iwanaga, N., Funahashi, A., Hiroi, N., Kitano, H. & Amano, H., 2006 Dec 1, Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL. p. 227-232 6 p. 4100980. (Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    6 Citations (Scopus)
  • A switch-tagged VLAN routing methodology for PC clusters with Ethernet

    Otsuka, T., Koibuchi, M., Kudoh, T. & Amano, H., 2006, ICPP 2006: Proceedings of the 2006 International Conference on Parallel Processing. p. 479-486 8 p. 1690652. (Proceedings of the International Conference on Parallel Processing).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    13 Citations (Scopus)
  • DIMMnet-2: A reconfigurable board connected into a memory slot

    Miyashiro, T., Kitamura, A., Yoshimi, M., Amano, H., Nakajyo, H. & Tanabe, N., 2006 Dec 1, Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL. p. 825-828 4 p. 4101085. (Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    1 Citation (Scopus)
  • Enforcing dimension-order routing in on-chip torus networks without virtual channels

    Matsutani, H., Koibuchi, M. & Amano, H., 2006, Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Springer Verlag, Vol. 4330. p. 207-218 12 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 4330).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    1 Citation (Scopus)
  • Hardware support for MPI in DIMMnet-2 network interface

    Tanabe, N., Kitamura, A., Miyashiro, T., Miyabe, Y., Araki, T., Luo, Z., Nakajo, H. & Amano, H., 2006, Proceedings - International Workshop on Innovative Architecture for Future Generation High Performance Processors and Systems, IWIA 2006. p. 73-80 8 p. 4089358. (Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    5 Citations (Scopus)
  • Performance/cost trade-off evaluation for the DCT implementation on the dynamically reconfigurable processor

    Tuan, V. M., Hasegawa, Y., Katsura, N. & Amano, H., 2006 Jan 1, Reconfigurable Computing: Architectures and Applications - Second International Workshop, ARC 2006, Revised Selected Papers. Springer Verlag, p. 115-121 7 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 3985 LNCS).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    1 Citation (Scopus)
  • Performance and power analysis of time-multiplexed execution on dynamically reconfigurable processor

    Hasegawa, Y., Abe, S., Kurotaki, S., Tuan, V. M., Katsura, N., Nakamura, T., Nishimura, T. & Amano, H., 2006, 20th International Parallel and Distributed Processing Symposium, IPDPS 2006. IEEE Computer Society, 1639431. (20th International Parallel and Distributed Processing Symposium, IPDPS 2006; vol. 2006).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    2 Citations (Scopus)
  • Performance evaluation of an FPGA-based biochemical simulator ReCSiP

    Osana, Y., Yoshimi, M., Iwaoka, Y., Kojima, T., Nishikawa, Y., Funahashi, A., Hiroi, N., Kitano, H., Amano, H., Shibata, Y. & Iwanaga, N., 2006 Dec 1, Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL. p. 845-850 6 p. 4101089. (Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    4 Citations (Scopus)
  • 2005

    A framework for ODE-based multimodel biochemical simulations on an FPGA

    Osana, Y., Fukushima, T., Yoshimi, M., Iwaoka, Y., Funahashi, A., Hiroi, N., Shibata, Y., Iwanaga, N., Kitano, H. & Amano, H., 2005 Dec 1, Proceedings - 2005 International Conference on Field Programmable Logic and Applications, FPL. p. 574-577 4 p. 1515788. (Proceedings - 2005 International Conference on Field Programmable Logic and Applications, FPL; vol. 2005).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    3 Citations (Scopus)
  • An adaptive cryptographic accelerator for IPsec on dynamically reconfigurable processor

    Hasegawa, Y., Abe, S., Matsutani, H., Amano, H., Anjo, K. & Awashima, T., 2005, Proceedings - 2005 IEEE International Conference on Field Programmable Technology. p. 163-170 8 p. 1568541. (Proceedings - 2005 IEEE International Conference on Field Programmable Technology; vol. 2005).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    17 Citations (Scopus)
  • An FPGA-based, multi-model simulation method for biochemical systems

    Osana, Y., Fukushima, T., Yoshimi, M., Iwaoka, Y., Funahashi, A., Hiroi, N., Shibata, Y., Kitano, H. & Amano, H., 2005, Proceedings - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005. 1420035. (Proceedings - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005; vol. 2005).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    5 Citations (Scopus)
  • An I/O mechanism on a dynamically reconfigurable processor - Which should be moved: Data or configuration?

    Amano, H., Abe, S., Deguchi, K. & Hasegawa, Y., 2005 Dec 1, Proceedings - 2005 International Conference on Field Programmable Logic and Applications, FPL. p. 347-352 6 p. 1515746. (Proceedings - 2005 International Conference on Field Programmable Logic and Applications, FPL; vol. 2005).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    4 Citations (Scopus)
  • A packet forwarding layer for DIMMnet and its hardware implementation

    Hamada, Y., Nishi, H., Kitamura, A., Tanabe, N., Amano, H. & Nakajo, H., 2005 Dec 1, Proceedings of the 2005 International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA'05. p. 461-467 7 p. (Proceedings of the 2005 International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA'05; vol. 2).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • Destination bundle: A routing table reduction technique for distributed routing on dependablenetworks-on-chips

    Matsutani, H., Koibuchi, M. & Amano, H., 2005 Dec 1, Proceedings of the 2005 International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA'05. p. 1343-1349 7 p. (Proceedings of the 2005 International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA'05; vol. 3).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • Efficient scheduling of rate law functions for ODE-based multimodel biochemical simulation on an FPGA

    Iwanagra, N., Shibata, Y., Yoshimi, M., Osana, Y., Iwaoka, Y., Fukushima, T., Amano, H., Funahashi, A., Hiroi, N., Kitano, H. & Oguri, K., 2005 Dec 1, Proceedings - 2005 International Conference on Field Programmable Logic and Applications, FPL. p. 666-669 4 p. 1515809. (Proceedings - 2005 International Conference on Field Programmable Logic and Applications, FPL; vol. 2005).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    10 Citations (Scopus)
  • Evaluation of network interface controller on DIMMnet-2 prototype board

    Kitamura, A., Hamada, Y., Miyabe, Y., Izawa, T., Miyashiro, T., Watanabe, K., Otsuka, T., Tanabe, N., Nakajo, H. & Amano, H., 2005 Dec 1, Proceedings - Sixth International Conference on Parallel and Distributed Computing, Applications and Technologies, PDCAT 2005. p. 778-780 3 p. 1579028. (Parallel and Distributed Computing, Applications and Technologies, PDCAT Proceedings; vol. 2005).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    2 Citations (Scopus)
  • Implementation of active direction-pass filter on dynamically reconfigurable processor

    Kurotaki, S., Suzuki, N., Nakadai, K., Okuno, H. G. & Amano, H., 2005, 2005 IEEE/RSJ International Conference on Intelligent Robots and Systems, IROS. IEEE Computer Society, p. 3175-3180 6 p. 1545033. (2005 IEEE/RSJ International Conference on Intelligent Robots and Systems, IROS).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    7 Citations (Scopus)
  • Implementation of ISIS-simplescalar

    Hanawa, T., Minai, T., Tanabe, Y. & Amano, H., 2005, Proceedings of the 2005 International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA'05. p. 117-123 7 p. (Proceedings of the 2005 International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA'05; vol. 1).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • Performance and cost analysis of time-multiplexed execution on the dynamically reconfigurable processor

    Amano, H., Abe, S., Hasegawa, Y., Deguchi, K. & Suzuki, M., 2005 Dec 1, Proceedings - 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2005. p. 315-316 2 p. 1508569. (Proceedings - 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2005; vol. 2005).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    8 Citations (Scopus)
  • Preliminary evaluations of a FPGA-based-prototype of DIMMnet-2 network interface

    Tanabe, N., Kitamura, A., Miyashiro, T., Miyabe, Y., Izawa, T., Hamada, Y., Nakajo, H. & Amano, H., 2005, IWIA 2005: Innovative Architecture for Future Generation High-Performance Processors and Systems. IEEE Computer Society, p. 9-17 9 p. 1587833. (Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems; vol. 2005).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    8 Citations (Scopus)
  • RoMultiC: Fast and simple configuration data multicasting scheme for coarse grain reconfigurable devices

    Tunbunheng, V., Suzuki, M. & Amano, H., 2005, Proceedings - 2005 IEEE International Conference on Field Programmable Technology. p. 129-136 8 p. 1568536. (Proceedings - 2005 IEEE International Conference on Field Programmable Technology; vol. 2005).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    39 Citations (Scopus)
  • The design of scalable stochastic biochemical simulator on FPGA

    Yoshimi, M., Osana, Y., Iwaoka, Y., Funahashi, A., Hiroi, N., Shibata, Y., Iwanaga, N., Kitano, H. & Amano, H., 2005, Proceedings - 2005 IEEE International Conference on Field Programmable Technology. p. 339-340 2 p. 1568590. (Proceedings - 2005 IEEE International Conference on Field Programmable Technology; vol. 2005).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    6 Citations (Scopus)
  • VLAN-based minimal paths in PC cluster with ethernet on mesh and torus

    Otsuka, T., Koibuchi, M., Jouraku, A. & Amano, H., 2005 Dec 1, Proceedings - 2005 International Conference on Parallel Processing. p. 567-576 10 p. 1488655. (Proceedings of the International Conference on Parallel Processing; vol. 2005).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    7 Citations (Scopus)
  • 2004

    A new memory module for memory intensive applications

    Tanabe, N., Hakozaki, H., Nakatake, M., Dohi, Y., Nakajo, H. & Amano, H., 2004 Dec 1, International Conference on Parallel Computing in Electrical Engineering: Workshop on System Design Automation, SDA, PARELEC 2004. p. 123-128 6 p. (International Conference on Parallel Computing in Electrical Engineering: Workshop on System Design Automation, SDA, PARELEC 2004).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    2 Citations (Scopus)
  • Black-bus: A new data-transfer technique using local address on networks-on-chips

    Anjo, K., Yamada, Y., Koibuchi, M., Jouraku, A. & Amano, H., 2004 Dec 1, Proceedings - 18th International Parallel and Distributed Processing Symposium, IPDPS 2004 (Abstracts and CD-ROM). p. 115-122 8 p. (Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2004 (Abstracts and CD-ROM); vol. 18).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    8 Citations (Scopus)
  • Implementing and evaluating stream applications on the dynamically reconfigurable processor

    Suzuki, N., Kurotaki, S., Suzuki, M., Kaneko, N., Yamada, Y., Deguchi, K., Hasegawa, Y., Amano, H., Anjo, K., Motomura, M., Wakabayashi, K., Toi, T. & Awashima, T., 2004 Dec 1, Proceedings - 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2004. Arnold, J. & Pocek, K. L. (eds.). p. 328-329 2 p. (Proceedings - 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2004).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    12 Citations (Scopus)
  • Stream applications on the dynamically reconfigurable processor

    Suzuki, M., Hasegawa, Y., Yamada, Y., Kaneko, N., Deguchi, K., Amano, H., Anjo, K., Motomura, M., Wakabayashi, K., Toi, T. & Awashima, T., 2004 Dec 1, Proceedings - 2004 IEEE International Conference on Field-Programmable Technology, FPT '04. Diessel, O. & Williams, J. (eds.). p. 137-144 8 p. (Proceedings - 2004 IEEE International Conference on Field-Programmable Technology, FPT '04).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    33 Citations (Scopus)
  • 2003

    An implementation of the Rijndael on Async-WASMII

    Adachi, Y., Ishikawa, K., Tsutsumi, S. & Amano, H., 2003 Jan 1, Proceedings - 2003 IEEE International Conference on Field-Programmable Technology, FPT 2003. Institute of Electrical and Electronics Engineers Inc., p. 44-51 8 p. 1275730. (Proceedings - 2003 IEEE International Conference on Field-Programmable Technology, FPT 2003).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    5 Citations (Scopus)
  • Descending layers routing: A deadlock-free deterministic routing using virtual channels in system area networks with irregular topologies

    Koibuchi, M., Jouraku, A., Watanabe, K. & Amano, H., 2003, Proceedings - 2003 International Conference on Parallel Processing, ICPP 2003. Sadayappan, P. & Yang, C-S. (eds.). Institute of Electrical and Electronics Engineers Inc., p. 527-536 10 p. 1240620. (Proceedings of the International Conference on Parallel Processing; vol. 2003-January).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    22 Citations (Scopus)
  • MAPLE chip: A processing element for a static scheduling centric multiprocessor

    Yasufuku, K., Ogawa, R., Iwai, K. & Amano, H., 2003, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Institute of Electrical and Electronics Engineers Inc., Vol. 2003-January. p. 575-576 2 p. 1195085

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • Performance evaluation of 3-dimensional MIN with cache consistency maintenance mechanism

    Tanabe, Y., Midorikawa, T., Shiraishi, D., Shigeno, M., Hanawa, T. & Amano, H., 2003, Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA 2003. Arabnia, H. R., Mun, Y., Arabnia, H. R. & Mun, Y. (eds.). p. 1148-1154 7 p. (Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications; vol. 3).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    1 Citation (Scopus)
  • Performance Evaluation of a Prototype of RHiNET-2: A Network-based Distributed Parallel Computing System

    Otsuka, T., Watanabe, K., Tsuchiya, J. I., Harada, H., Yamamoto, J., Nishi, H., Kudoh, T. & Amano, H., 2003 Dec 1, 21st IASTED International Multi-Conference on Applied Informatics. p. 738-743 6 p. (IASTED International Multi-Conference on Applied Informatics; vol. 21).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    7 Citations (Scopus)
  • Performance evaluation of instruction set architecture of MBP-light: A distributed memory controller for a large scale multiprocessor

    Suzuki, N. & Amano, H., 2003 Dec 1, Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA 2003. Arabnia, H. R., Mun, Y., Arabnia, H. R. & Mun, Y. (eds.). p. 1155-1161 7 p. (Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications; vol. 3).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • Performance evaluation of RHiNET 2/NI: A network interface for distributed parallel computing systems

    Watanabe, K., Otsuka, T., Tsuchiya, J. I., Amano, H., Harada, H., Yamamoto, J., Nishi, H. & Kudoh, T., 2003 Dec 1, Proceedings - CCGrid 2003: 3rd IEEE/ACM International Symposium on Cluster Computing and the Grid. p. 318-325 8 p. 1199383. (Proceedings - CCGrid 2003: 3rd IEEE/ACM International Symposium on Cluster Computing and the Grid).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    10 Citations (Scopus)
  • Performance evaluation of routing algorithms in RHiNET-2 cluster

    Koibuchi, M., Watanabe, K., Kono, K., Jouraku, A. & Amano, H., 2003 Jan 1, Proceedings - IEEE International Conference on Cluster Computing, CLUSTER 2003. Institute of Electrical and Electronics Engineers Inc., p. 395-402 8 p. 1253339. (Proceedings - IEEE International Conference on Cluster Computing, ICCC; vol. 2003-January).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    15 Citations (Scopus)
  • Prototyping on using a DIMM slot as a high-performance I/O interface

    Tanabe, N., Hamada, Y., Mitsuhashi, A., Nakajo, H., Yamamoto, J., Imashiro, H., Kudoh, T. & Amano, H., 2003, Innovative Architecture for Future Generation High-Performance Processors and Systems, IWIA 2003. Veidenbaum, A. & Joe, K. (eds.). IEEE Computer Society, p. 108-116 9 p. 1262788. (Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems; vol. 2003-January).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    3 Citations (Scopus)
  • The evaluation of dynamic load balancing algorithm on RHiNET-2

    Kitamura, A., Watanabe, K., Otsuka, T. & Amano, H., 2003, Proceedings of the Fifteenth IASTED International Conference on Parallel and Distributed Computing and Sytems. Gonzalez, T. (ed.). 1 ed. p. 262-267 6 p. (Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Systems; vol. 15, no. 1).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • 2002

    A general hardware design model for multicontext FPGAs

    Kaneko, N. & Amano, H., 2002 Dec 1, Field-Programmable Logic and Applications: Reconfigurable Computing is Going Mainstream - 12th International Conference, FPL 2002, Proceedings. p. 1037-1047 11 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 2438 LNCS).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    3 Citations (Scopus)
  • A low latency high bandwidth network interface prototype for PC cluster

    Tanabe, N., Hamada, Y., Nakajo, H., Imashiro, H., Yamamoto, J., Kudoh, T. & Amano, H., 2002, International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems, IWIA 2002. Joe, K. & Veidenbaum, A. (eds.). IEEE Computer Society, p. 87-94 8 p. 1035022. (Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems; vol. 2002-January).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    7 Citations (Scopus)
  • RHiNET/NI: A reconfigurable network interface for cluster computing

    Izu, N., Yokoyama, T., Tsuchiya, J., Watanabe, K. & Amano, H., 2002, Field-Programmable Logic and Applications: Reconfigurable Computing is Going Mainstream - 12th International Conference, FPL 2002, Proceedings. Springer Verlag, p. 1118-1121 4 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 2438 LNCS).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • Routing algorithms based on 2D turn model for irregular networks

    Jouraku, A., Koibuchi, M., Amano, H. & Funahashi, A., 2002, Proceedings - International Symposium on Parallel Architectures, Algorithms and Networks, I-SPAN 2002. Hsu, D. F., Saldana, R. P. & Ibarra, O. H. (eds.). IEEE Computer Society, p. 289-294 6 p. 1004296. (Proceedings of the International Symposium on Parallel Architectures, Algorithms and Networks, I-SPAN; vol. 2002-January).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    13 Citations (Scopus)
  • 2001

    A prototype chip of multicontext FPGA with DRAM for virtual hardware

    Kawakami, D., Shibata, Y. & Amano, H., 2001 Jan 1, Proceedings of the ASP-DAC 2001: Asia and South Pacific Design Automation Conference 2001. Institute of Electrical and Electronics Engineers Inc., p. 17-18 2 p. 913267. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; vol. 2001-January).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    7 Citations (Scopus)
  • L-turn routing: An adaptive routing in irregular networks

    Koibuchi, M., Funahashi, A., Jouraku, A. & Amano, H., 2001, Proceedings of the International Conference on Parallel Processing. Institute of Electrical and Electronics Engineers Inc., Vol. 2001-January. p. 383-392 10 p. 952084

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    49 Citations (Scopus)
  • RHiNET-3/SW: An 80-Gbit/s high-speed network switch for distributed parallel computing

    Nishimura, S., Kudoh, T., Nishi, H., Yamamoto, J., Ueno, R., Harasawa, K., Fukuda, S., Shikichi, Y., Akutsu, S., Tasho, K. & Amano, H., 2001 Jan 1, HOT Interconnects 9, HIS 2001. Institute of Electrical and Electronics Engineers Inc., p. 119-123 5 p. 946703. (Proceedings - Symposium on the High Performance Interconnects, Hot Interconnects; vol. 2001-January).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    7 Citations (Scopus)
  • 2000

    A local area system network RHiNET-1: A network for high performance parallel computing

    Nishi, H., Tasho, K., Yamamoto, J., Kudoh, T. & Amano, H., 2000 Jan 1, Proceedings - The 9th International Symposium on High-Performance Distributed Computing, HPDC 2000. Institute of Electrical and Electronics Engineers Inc., p. 296-297 2 p. 868665. (Proceedings of the IEEE International Symposium on High Performance Distributed Computing; vol. 2000-January).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    1 Citation (Scopus)
  • A reconfigurable stochastic model simulator for analysis of parallel systems

    Yamamoto, O., Shibata, Y., Kurosawa, H. & Amano, H., 2000, IEEE Symposium on FPGAs for Custom Computing Machines, Proceedings. Institute of Electrical and Electronics Engineers Inc., Vol. 2000-January. p. 291-292 2 p. 903422

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    2 Citations (Scopus)
  • A reconfigurable stochastic model simulator for analysis of parallel systems

    Yamamoto, O., Shibata, Y., Kurosawa, H. & Amano, H., 2000, Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing - 10th International Conference, FPL 2000, Proceedings. Hartenstein, R. W. & Grunbacher, H. (eds.). Springer Verlag, p. 475-484 10 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 1896).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution