• 2531 Citations
  • 23 h-Index
1983 …2020

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(SM)2-II: A Large-Scale Multiprocessor for Sparse Matrix Calculations

Amano, H., Boku, T. & Kudoh, T., 1990 Jul, In : IEEE Transactions on Computers. 39, 7, p. 889-905 17 p.

Research output: Contribution to journalArticle

2 Citations (Scopus)

3D NoC with inductive-coupling links for building-block SiPs

Take, Y., Matsutani, H., Sasaki, D., Koibuchi, M., Kuroda, T. & Amano, H., 2014 Mar, In : IEEE Transactions on Computers. 63, 3, p. 748-763 16 p., 6331480.

Research output: Contribution to journalArticle

34 Citations (Scopus)

64-Gb/s highly reliable network switch (RHiNET-2/SW) using parallel optical interconnection

Nishimura, S., Kudoh, T., Nishi, H., Yamamoto, J., Harasawa, K., Matsudaira, N., Akutsu, S. & Amano, H., 2000 Dec 1, In : Journal of Lightwave Technology. 18, 12, p. 1620-1627 8 p.

Research output: Contribution to journalArticle

6 Citations (Scopus)

A Dynamically Adaptive Hardware on Dynamically Reconfigurable Processor

Amano, H., Jouraku, A. & Anjo, K., 2003 Dec, In : IEICE Transactions on Communications. E86-B, 12, p. 3385-3391 7 p.

Research output: Contribution to journalArticle

10 Citations (Scopus)
6 Citations (Scopus)

A fine-grained multicasting of configuration data for coarse-grained reconfigurable architectures

Kojima, T. & Amano, H., 2019 Jan 1, In : IEICE Transactions on Information and Systems. E102D, 7, p. 1247-1256 10 p.

Research output: Contribution to journalArticle

Open Access

A fine-grained power gating control on linux monitoring power consumption of processor functional units

Koshiba, A., Wada, M., Sakamoto, R., Sato, M., Kosaka, T., Usami, K., Amano, H., Kondo, M., Nakamura, H. & Namiki, M., 2015 Jul 1, In : IEICE Transactions on Electronics. E98C, 7, p. 559-568 10 p.

Research output: Contribution to journalArticle

2 Citations (Scopus)

A generalized theory based on the turn model for deadlock-free irregular networks

Kawano, R., Yasudo, R., Matsutani, H., Koibuchi, M. & Amano, H., 2020 Jan 1, In : IEICE Transactions on Information and Systems. E103D, 1, p. 101-110 10 p.

Research output: Contribution to journalArticle

Open Access

A layout-oriented routing method for low-latency HPC networks

Kawano, R., Nakahara, H., Fujiwara, I., Matsutani, H., Koibuchi, M. & Amano, H., 2017 Dec 1, In : IEICE Transactions on Information and Systems. E100D, 12, p. 2796-2807 12 p.

Research output: Contribution to journalArticle

1 Citation (Scopus)

A leakage efficient data TLB design for embedded processors

Lei, Z., Xu, H., Ikebuchi, D., Sunata, T., Namiki, M. & Amano, H., 2011 Jan, In : IEICE Transactions on Information and Systems. E94-D, 1, p. 51-59 9 p.

Research output: Contribution to journalArticle

Open Access

A leakage efficient instruction TLB design for embedded processors

Lei, Z., Xu, H., Ikebuchi, D., Sunata, T., Namiki, M. & Amano, H., 2011 Aug, In : IEICE Transactions on Information and Systems. E94-D, 8, p. 1565-1574 10 p.

Research output: Contribution to journalArticle

A link removal methodology for application-specific networks-on-chip on FPGAs

Wang, D., Matsutani, H., Koibuchi, M. & Amano, H., 2009 Jan 1, In : IEICE Transactions on Information and Systems. E92-D, 4, p. 575-583 9 p.

Research output: Contribution to journalArticle

A mapping method for multi-process execution on dynamically reconfigurable processors

Manh Tuan, V. & Amano, H., 2008 Sep, In : IEICE Transactions on Information and Systems. E91-D, 9, p. 2312-2322 11 p.

Research output: Contribution to journalArticle

4 Citations (Scopus)

Analysis of body bias control using overhead conditions for real time systems: A practical approach

Torres, C. C. C., Okuhara, H., Yamasaki, N. & Amano, H., 2018 Apr 1, In : IEICE Transactions on Information and Systems. E101D, 4, p. 1116-1125 10 p.

Research output: Contribution to journalArticle

1 Citation (Scopus)

An analysis of fairness and overhead in the arbitration protocol of the IEEE futurebus standard

Yamamoto, O., Terasawa, T. & Amano, H., 1998 Nov 30, In : Systems and Computers in Japan. 29, 13, p. 66-77 12 p.

Research output: Contribution to journalArticle

An analytical network performance model for SIMD processor CSX600 interconnects

Nishikawa, Y., Koibuchi, M., Yoshimi, M., Miura, K. & Amano, H., 2011 Jan 1, In : Journal of Systems Architecture. 57, 1, p. 146-159 14 p.

Research output: Contribution to journalArticle

An effective design of deadlock-free routing algorithms based on 2D turn model for irregular networks

Jouraku, A., Koibuchi, M. & Amano, H., 2007 Mar 1, In : IEEE Transactions on Parallel and Distributed Systems. 18, 3, p. 320-333 14 p.

Research output: Contribution to journalArticle

25 Citations (Scopus)

A network switch for supporting high-performance parallel processing by computers distributed in local areas

Nishi, H., Tasho, K., Kudoh, T. & Amano, H., 2001 Dec 1, In : Systems and Computers in Japan. 32, 14, p. 24-33 10 p.

Research output: Contribution to journalArticle

An operating system guided fine-grained power gating control based on runtime characteristics of applications

Koshiba, A., Sato, M., Usami, K., Amano, H., Sakamoto, R., Kondo, M., Nakamura, H. & Namiki, M., 2016 Aug 1, In : IEICE Transactions on Electronics. E99C, 8, p. 926-935 10 p.

Research output: Contribution to journalArticle

A novel channel assignment method to ensure deadlock-freedom for deterministic routing

Kawano, R., Nakahara, H., Tade, S., Fujiwara, I., Matsutani, H., Koibuchi, M. & Amano, H., 2017 Aug 1, In : IEICE Transactions on Information and Systems. E100D, 8, p. 1798-1806 9 p.

Research output: Contribution to journalArticle

2 Citations (Scopus)

A performance evaluation of the multiprocessor testbed ATTEMPT-0

Terasawa, T., Yamamoto, O., Kudoh, T. & Amano, H., 1995 May, In : Parallel Computing. 21, 5, p. 701-730 30 p.

Research output: Contribution to journalArticle

2 Citations (Scopus)

A perpetuum mobile 32bit CPU on 65nm SOTB CMOS technology with reverse-body-bias assisted sleep mode

Ishibashi, K., Sugii, N., Kamohara, S., Usami, K., Amano, H., Kobayashi, K. & Pham, C. K., 2015 Jul 1, In : IEICE Transactions on Electronics. E98C, 7, p. 536-543 8 p.

Research output: Contribution to journalArticle

17 Citations (Scopus)

A port combination methodology for application-specific networks-on-chip on FPGAS

Wang, D., Matsutani, H., Koibuchi, M. & Amano, H., 2007 Dec, In : IEICE Transactions on Information and Systems. E90-D, 12, p. 1914-1922 9 p.

Research output: Contribution to journalArticle

A preemption algorithm for a multitasking environment on dynamically reconfigurable processors

Tuan, V. M. & Amano, H., 2008 Jan 1, In : IEICE Transactions on Information and Systems. E91-D, 12, p. 2793-2803 11 p.

Research output: Contribution to journalArticle

A query‐based parallel logic simulation algorithm

Kudoh, T., Kimura, T., Amano, H. & Terasawa, T., 1993, In : Systems and Computers in Japan. 24, 2, p. 11-21 11 p.

Research output: Contribution to journalArticle

Architecture and Evaluation of a Third-Generation RHiNET Switch for High-Performance Parallel Computing

Nishi, H., Nishimura, S., Harasawa, K., Kudoh, T. & Amano, H., 2003 Oct, In : IEICE Transactions on Information and Systems. E86-D, 10, p. 1987-1995 9 p.

Research output: Contribution to journalArticle

A retargetable compiler based on graph representation for dynamically reconfigurable processor arrays

Tunbunheng, V. & Amano, H., 2008 Nov, In : IEICE Transactions on Information and Systems. E91-D, 11, p. 2655-2665 11 p.

Research output: Contribution to journalArticle

3 Citations (Scopus)

A routing algorithm for multihop WDM ring

Bong, X., Kudoh, T. & Amano, H., 1999 Jan 1, In : IEICE Transactions on Information and Systems. E82-D, 2, p. 422-430 9 p.

Research output: Contribution to journalArticle

A scalable 3D heterogeneous multicore with an inductive ThruChip interface

Miura, N., Koizumi, Y., Take, Y., Matsutani, H., Kuroda, T., Amano, H., Sakamoto, R., Namiki, M., Usami, K., Kondo, M. & Nakamura, H., 2013 Nov 1, In : IEEE Micro. 33, 6, p. 6-15 10 p., 6684194.

Research output: Contribution to journalArticle

21 Citations (Scopus)

A simple data transfer technique using local address for networks-on-chips

Koibuchi, M., Anjo, K., Yamada, Y., Jouraku, A. & Amano, H., 2006 Dec 1, In : IEEE Transactions on Parallel and Distributed Systems. 17, 12, p. 1425-1437 13 p.

Research output: Contribution to journalArticle

16 Citations (Scopus)

A study on snoop cache systems for single-chip multiprocessors

Terasawa, T., Inoue, K., Kurosawa, H. & Amano, H., 1998 Feb, In : Systems and Computers in Japan. 28, 2, p. 62-72 11 p.

Research output: Contribution to journalArticle

A switch-tagged routing methodology for PC clusters with VLAN Ethernet

Koibuchi, M., Otsuka, T., Kudoh, T. & Amano, H., 2011 Jan 1, In : IEEE Transactions on Parallel and Distributed Systems. 22, 2, p. 217-230 14 p., 5445093.

Research output: Contribution to journalArticle

4 Citations (Scopus)

Asymmetric Body Bias Control With Low-Power FD-SOI Technologies: Modeling and Power Optimization

Okuhara, H., Ben Ahmed, A., Kuhn, J. M. & Amano, H., 2018 Mar 23, (Accepted/In press) In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Research output: Contribution to journalArticle

8 Citations (Scopus)

A toolchain for dynamic function off-load on CPU-FPGA platforms

Miyajima, T., Thomas, D. & Amano, H., 2015 Jan 1, In : Journal of information processing. 23, 2, p. 153-162 10 p.

Research output: Contribution to journalArticle

1 Citation (Scopus)

Automatic pipeline construction focused on similarity of rate law functions for an FPGA-based biochemical simulator

Yamada, H., Ogawa, Y., Ooya, T., Ishimori, T., Osana, Y., Yoshimi, M., Nishikawa, Y., Funahashi, A., Hiroi, N., Amano, H., Shibata, Y. & Oguri, K., 2010 Dec 1, In : IPSJ Transactions on System LSI Design Methodology. 3, p. 244-256 13 p.

Research output: Contribution to journalArticle

2 Citations (Scopus)

Body Bias Control for Renewable Energy Source with a High Inner Resistance

Azegami, K., Okuhara, H. & Amano, H., 2018 Apr 16, (Accepted/In press) In : IEEE Transactions on Multi-Scale Computing Systems.

Research output: Contribution to journalArticle

Body bias domain partitioning size exploration for a coarse grained reconfigurable accelerator

Matsushita, Y., Okuhara, H., Masuyama, K., Fujita, Y., Kawano, R. & Amano, H., 2017 Dec 1, In : IEICE Transactions on Information and Systems. E100D, 12, p. 2828-2836 9 p.

Research output: Contribution to journalArticle

Body bias optimization for real-time systems

Torres, C. C. C., Yasudo, R. & Amano, H., 2020 Mar, In : Journal of Low Power Electronics and Applications. 10, 1, 8.

Research output: Contribution to journalArticle

Open Access

Code compression with split echo instructions

Stubdal, I., Karaduman, A. & Amano, H., 2009 Jan 1, In : IEICE Transactions on Information and Systems. E92-D, 9, p. 1650-1656 7 p.

Research output: Contribution to journalArticle

1 Citation (Scopus)

COMPATIBLE ACKNOWLEDGING ETHERNET.

Saito, T., Tokoro, M. & Amano, H., 1987 Oct 1, In : Transactions of the Institute of Electronics, Information and Communication Engineers, Section E (. E70, 10, p. 960-967 8 p.

Research output: Contribution to journalArticle

Cool mega-arrays: Ultralow-power reconfigurable accelerator chips

Ozaki, N., Yasuda, Y., Izawa, M., Saito, Y., Ikebuchi, D., Amano, H., Nakamura, H., Usami, K., Namiki, M. & Kondo, M., 2011 Nov 1, In : IEEE Micro. 31, 6, p. 6-18 13 p., 6060791.

Research output: Contribution to journalArticle

37 Citations (Scopus)

Courier: A toolchain for application acceleration on heterogeneous platforms

Miyajima, T., Thomas, D. & Amano, H., 2015 Feb 1, In : IPSJ Transactions on System LSI Design Methodology. 8, p. 105-115 11 p.

Research output: Contribution to journalArticle

Data multicasting procedure for increasing configuration speed of coarse grain reconfigurable devices

Tunbunheng, V., Suzuki, M. & Amano, H., 2007 Feb, In : IEICE Transactions on Information and Systems. E90-D, 2, p. 473-481 9 p.

Research output: Contribution to journalArticle

1 Citation (Scopus)

Design and implementation fine-grained power gating on microprocessor functional units

Lei, Z., Ikebuchi, D., Usami, K., Namiki, M., Kondo, M., Nakamura, H. & Amano, H., 2011 Dec 5, In : IPSJ Transactions on System LSI Design Methodology. 4, p. 182-192 11 p.

Research output: Contribution to journalArticle

3 Citations (Scopus)

Design and implementation of echo instructions for an embedded processor

Arda, K., Iver, S. & Amano, H., 2011 Dec 5, In : IPSJ Transactions on System LSI Design Methodology. 4, p. 222-231 10 p.

Research output: Contribution to journalArticle

Design and implementation of reconfigurable sensing system for networked robots

Miyajima, A., Nukata, K., Amano, H. & Anzai, Y., 1998 Jan 1, In : Advanced Robotics. 13, 3, p. 253-254 2 p.

Research output: Contribution to journalArticle

Design and Implementation of RHiNET-2/NI0: A Reconfigurable Network Interface for Cluster Computing

Yokoyama, T., Izu, N., Tsuchiya, J. I., Watanabe, K., Amano, H. & Kudoh, T., 2003 May, In : IEICE Transactions on Information and Systems. E86-D, 5, p. 789-795 7 p.

Research output: Contribution to journalArticle

1 Citation (Scopus)

Designing High-Performance Interconnection Networks with Host-Switch Graphs

Yasudo, R., Koibuchi, M., Nakano, K., Matsutani, H. & Amano, H., 2018 Aug 6, (Accepted/In press) In : IEEE Transactions on Parallel and Distributed Systems.

Research output: Contribution to journalArticle

1 Citation (Scopus)