Calculated based on number of publications stored in Pure and citations from Scopus
20052022

Research activity per year

If you made any changes in Pure these will be visible here soon.
Filter
Conference contribution

Search results

  • 2005

    An adaptive cryptographic accelerator for IPsec on dynamically reconfigurable processor

    Hasegawa, Y., Abe, S., Matsutani, H., Amano, H., Anjo, K. & Awashima, T., 2005, Proceedings - 2005 IEEE International Conference on Field Programmable Technology. p. 163-170 8 p. 1568541. (Proceedings - 2005 IEEE International Conference on Field Programmable Technology; vol. 2005).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    18 Citations (Scopus)
  • Destination bundle: A routing table reduction technique for distributed routing on dependablenetworks-on-chips

    Matsutani, H., Koibuchi, M. & Amano, H., 2005 Dec 1, Proceedings of the 2005 International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA'05. p. 1343-1349 7 p. (Proceedings of the 2005 International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA'05; vol. 3).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • 2006

    A Virtual-Channel Free Mapping for Application-Specific On-Chip Torus Networks

    Matsutani, H., Koibuchi, M. & Amano, H., 2006, 19th International Conference on Parallel and Distributed Computing Systems 2006, PDCS 2006. International Society for Computers and Their Applications (ISCA), p. 24-31 8 p. (19th International Conference on Parallel and Distributed Computing Systems 2006, PDCS 2006).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    1 Citation (Scopus)
  • Enforcing dimension-order routing in on-chip torus networks without virtual channels

    Matsutani, H., Koibuchi, M. & Amano, H., 2006, Parallel and Distributed Processing and Applications - 4th International Symposium, ISPA 2006, Proceedings. Guo, M., Yang, L. T., Di Martino, B., Zima, H. P., Zima, H. P., Dongarra, J. & Tang, F. (eds.). Springer Verlag, p. 207-218 12 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 4330).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    1 Citation (Scopus)
  • 2007

    A temporal correlation based port combination methodology for Networks-on-Chip on reconfigurable systems

    Wang, D., Matsutani, H., Amano, H. & Koibuchi, M., 2007, Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL. p. 383-388 6 p. 4380676. (Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    4 Citations (Scopus)
  • Performance, cost, and energy evaluation of fat H-tree: A cost-efficient tree-based on-chip network

    Matsutani, H., Koibuchi, M. & Amano, H., 2007 Sep 24, Proceedings - 21st International Parallel and Distributed Processing Symposium, IPDPS 2007; Abstracts and CD-ROM. 4227999. (Proceedings - 21st International Parallel and Distributed Processing Symposium, IPDPS 2007; Abstracts and CD-ROM).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    22 Citations (Scopus)
  • Tightly-coupled multi-layer topologies for 3-D NoCs

    Matsutani, H., Koibuchi, M. & Amano, H., 2007, 2007 International Conference on Parallel Processing, ICPP. 4343882. (Proceedings of the International Conference on Parallel Processing).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    68 Citations (Scopus)
  • 2008

    Adding slow-silent virtual channels for low-power on-chip networks

    Matsutani, H., Koibuchi, M., Wang, D. & Amano, H., 2008, Proceedings - Second IEEE International Symposium on Networks-on-Chip, NOCS 2008. p. 23-32 10 p. 4492722. (Proceedings - Second IEEE International Symposium on Networks-on-Chip, NOCS 2008).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    38 Citations (Scopus)
  • A lightweight fault-tolerant mechanism for network-on-chip

    Koibuchi, M., Matsutani, H., Amano, H. & Pinkston, T. M., 2008 May 28, Proceedings - Second IEEE International Symposium on Networks-on-Chip, NOCS 2008. p. 13-22 10 p. 4492721. (Proceedings - Second IEEE International Symposium on Networks-on-Chip, NOCS 2008).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    116 Citations (Scopus)
  • A link removal methodology for networks-on-chip on reconfigurable systems

    Wang, D., Matsutani, H., Arnano, H. & Koibuchi, M., 2008 Nov 3, Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL. p. 269-274 6 p. 4629943. (Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    10 Citations (Scopus)
  • Run-time power gating of on-chip routers using look-ahead routing

    Matsutani, H., Koibuchi, M., Amano, H. & Wang, D., 2008, 2008 Asia and South Pacific Design Automation Conference, ASP-DAC. p. 55-60 6 p. 4484015. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    75 Citations (Scopus)
  • Three-dimensional layout of on-chip tree-based networks

    Matsutani, H., Koibuchi, M., Hsu, D. F. & Amano, H., 2008, Proceedings - 9th International Symposium on Parallel Architectures, Algorithms and Networks, I-SPAN 2008. p. 281-288 8 p. 4520228. (Proceedings of the International Symposium on Parallel Architectures, Algorithms and Networks, I-SPAN).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    12 Citations (Scopus)
  • 2009

    An on/off link activation method for low-power ethernet in PC clusters

    Koibuchi, M., Otsuka, T., Matsutani, H. & Amano, H., 2009, IPDPS 2009 - Proceedings of the 2009 IEEE International Parallel and Distributed Processing Symposium. 5161069. (IPDPS 2009 - Proceedings of the 2009 IEEE International Parallel and Distributed Processing Symposium).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    13 Citations (Scopus)
  • Balanced dimension-order routing for k-ary n-cubes

    Montañana, J. M., Koibuchi, M., Matsutani, H. & Amano, H., 2009, ICPPW 2009 - The 38th International Conference Parallel Processing Workshops. p. 499-506 8 p. 5365405. (Proceedings of the International Conference on Parallel Processing Workshops).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    12 Citations (Scopus)
  • Evaluation of a multicore reconfigurable architecture with variable core sizes

    Tuan, V. M., Katsura, N., Matsutani, H. & Amano, H., 2009 Nov 25, IPDPS 2009 - Proceedings of the 2009 IEEE International Parallel and Distributed Processing Symposium. 5161225. (IPDPS 2009 - Proceedings of the 2009 IEEE International Parallel and Distributed Processing Symposium).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    4 Citations (Scopus)
  • MuCCRA-Cube: A 3D dynamically reconfigurable processor with inductive-coupling link

    Saito, S., Kohama, Y., Sugimori, Y., Hasegawa, Y., Matsutani, H., Sano, T., Kasuga, K., Yoshida, Y., Niitsu, K., Miura, N., Kuroda, T. & Amano, H., 2009 Nov 25, FPL 09: 19th International Conference on Field Programmable Logic and Applications. p. 6-11 6 p. 5272565. (FPL 09: 19th International Conference on Field Programmable Logic and Applications).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    22 Citations (Scopus)
  • Prediction router: Yet another low latency on-chip router architecture

    Matsutani, H., Koibuchi, M., Amano, H. & Yoshinaga, T., 2009, Proceedings - 15th International Symposium on High-Performance Computer Architecture, HPCA - 15 2009. IEEE Computer Society, p. 367-378 12 p. 4798274. (Proceedings - International Symposium on High-Performance Computer Architecture).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    67 Citations (Scopus)
  • 2010

    A deadlock-free non-minimal fully adaptive routing using virtual cut-through switching

    Nishikawa, Y., Koibuchi, M., Matsutani, H. & Amano, H., 2010 Oct 27, Proceedings - 2010 IEEE International Conference on Networking, Architecture and Storage, NAS 2010. p. 431-438 8 p. 5575700. (Proceedings - 2010 IEEE International Conference on Networking, Architecture and Storage, NAS 2010).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    1 Citation (Scopus)
  • A low-power fault-tolerant noc using error correction and detection codes

    Kojima, Y., Matsutani, H., Koibuchi, M. & Amano, H., 2010 Jan 1, Proceedings of the 9th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2010. Acta Press, p. 111-118 8 p. (Proceedings of the 9th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2010).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • An efficient path setup for a hybrid photonic Network-on-Chip

    Adi, C. A. D., Matsutani, H., Koibuchi, M., Irie, H., Miyoshi, T. & Yoshinaga, T., 2010 Dec 1, Proceedings - 2010 1st International Conference on Networking and Computing, ICNC 2010. p. 156-161 6 p. 5695227. (Proceedings - 2010 1st International Conference on Networking and Computing, ICNC 2010).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    6 Citations (Scopus)
  • A variable-pipeline on-chip router optimized to traffic pattern

    Hirata, Y., Matsutani, H., Koibuchi, M. & Amano, H., 2010, 3rd International Workshop on Network on Chip Architectures, NoCArc 2010, in Conjunction with the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-43. p. 57-62 6 p. (3rd International Workshop on Network on Chip Architectures, NoCArc 2010, in Conjunction with the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-43).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    7 Citations (Scopus)
  • Performance, cost, and power evaluations of on-chip network topologies in FPGAs

    In, S., Matsutani, H., Koibuchi, M., Wang, D. & Amano, H., 2010 Jul 20, Proceedings of the 9th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2010. p. 181-189 9 p. (Proceedings of the 9th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2010).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • Stabilizing Path Modification of Power-Aware On/Off Interconnection Networks

    Montañana, J. M., Koibuchi, M., Matsutani, H. & Amano, H., 2010, Proceedings - 2010 IEEE International Conference on Networking, Architecture and Storage, NAS 2010. p. 218-227 10 p. 5575649. (Proceedings - 2010 IEEE International Conference on Networking, Architecture and Storage, NAS 2010).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • Ultra fine-grained run-time power gating of on-chip routers for CMPs

    Matsutani, H., Koibuchi, M., Ikebuchi, D., Usami, K., Nakamura, H. & Amano, H., 2010, NOCS 2010 - The 4th ACM/IEEE International Symposium on Networks-on-Chip. p. 61-68 8 p. 5507560. (NOCS 2010 - The 4th ACM/IEEE International Symposium on Networks-on-Chip).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    58 Citations (Scopus)
  • 2011

    A dynamic link-width optimization for network-on-chip

    Wang, D., Koibuchi, M., Yoneda, T., Matsutani, H. & Amano, H., 2011 Dec 1, Proceedings - 1st International Workshop on Cyber-Physical Systems, Networks, and Applications, CPSNA 2011, Workshop Held During RTCSA 2011. p. 106-108 3 p. 602900. (Proceedings - 1st International Workshop on Cyber-Physical Systems, Networks, and Applications, CPSNA 2011, Workshop Held During RTCSA 2011; vol. 2).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    1 Citation (Scopus)
  • A vertical bubble flow network using inductive-coupling for 3-D CMPs

    Matsutani, H., Take, Y., Sasaki, D., Kimura, M., Ono, Y., Nishiyama, Y., Koibuchi, M., Kuroda, T. & Amano, H., 2011, NOCS 2011: The 5th ACM/IEEE International Symposium on Networks-on-Chip. p. 49-56 8 p. (NOCS 2011: The 5th ACM/IEEE International Symposium on Networks-on-Chip).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    17 Citations (Scopus)
  • Design and implementation of on-chip adaptive router with predictor for regional congestion

    Taniguchi, M., Matsutani, H. & Yamasaki, N., 2011 Dec 1, Proceedings - 1st International Workshop on Cyber-Physical Systems, Networks, and Applications, CPSNA 2011, Workshop Held During RTCSA 2011. p. 22-27 6 p. 602904. (Proceedings - 1st International Workshop on Cyber-Physical Systems, Networks, and Applications, CPSNA 2011, Workshop Held During RTCSA 2011; vol. 2).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    3 Citations (Scopus)
  • Dynamic Voltage and Frequency Scaling for real-time scheduling on a prioritized SMT processor

    Fujii, K., Chishiro, H., Matsutani, H. & Yamasaki, N., 2011 Dec 1, Proceedings - 1st International Workshop on Cyber-Physical Systems, Networks, and Applications, CPSNA 2011, Workshop Held During RTCSA 2011. p. 9-15 7 p. 602902. (Proceedings - 1st International Workshop on Cyber-Physical Systems, Networks, and Applications, CPSNA 2011, Workshop Held During RTCSA 2011; vol. 2).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    5 Citations (Scopus)
  • Performance evaluation of power-aware multi-tree ethernet for HPC interconnects

    Koibuchi, M., Watanabe, T., Minamihata, A., Nakao, M., Hiroyasu, T., Matsutani, H. & Amano, H., 2011, Proceedings - 2011 2nd International Conference on Networking and Computing, ICNC 2011. p. 50-57 8 p. 6131793. (Proceedings - 2011 2nd International Conference on Networking and Computing, ICNC 2011).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    1 Citation (Scopus)
  • 2012

    A case for random shortcut topologies for HPC interconnects

    Koibuchi, M., Matsutani, H., Amano, H., Hsu, D. F. & Casanova, H., 2012, 2012 39th Annual International Symposium on Computer Architecture, ISCA 2012. p. 177-188 12 p. 6237016. (Proceedings - International Symposium on Computer Architecture).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    100 Citations (Scopus)
  • A multi-Vdd dynamic variable-pipeline on-chip router for CMPs

    Matsutani, H., Hirata, Y., Koibuchi, M., Usami, K., Nakamura, H. & Amano, H., 2012, ASP-DAC 2012 - 17th Asia and South Pacific Design Automation Conference. p. 407-412 6 p. 6164982. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    16 Citations (Scopus)
  • CMA-Cube: A scalable reconfigurable accelerator with 3-D wireless inductive coupling interconnect

    Koizumi, Y., Sasaki, E., Amano, H., Matsutani, H., Take, Y., Kuroda, T., Sakamoto, R., Namiki, M., Usami, K., Kondo, M. & Nakamura, H., 2012 Dec 12, Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012. p. 543-546 4 p. 6339375. (Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    6 Citations (Scopus)
  • Dependable Responsive Multithreaded Processor for distributed real-time systems

    Suito, K., Fujii, K., Matsutani, H. & Yamasaki, N., 2012 Jul 25, Symposium on Low-Power and High-Speed Chips - Proceedings for 2012 IEEE COOL Chips XV. 6216589. (Symposium on Low-Power and High-Speed Chips - Proceedings for 2012 IEEE COOL Chips XV).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    4 Citations (Scopus)
  • Dynamic power control with a heterogeneous multi-core system using a 3-D wireless inductive coupling interconnect

    Koizumi, Y., Amano, H., Matsutani, H., Miura, N., Kuroda, T., Sakamoto, R., Namiki, M., Usami, K., Kondo, M. & Nakamura, H., 2012 Dec 1, FPT 2012 - 2012 International Conference on Field-Programmable Technology. p. 293-296 4 p. 6412150. (FPT 2012 - 2012 International Conference on Field-Programmable Technology).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    7 Citations (Scopus)
  • Vertical link on/off control methods for wireless 3-D NoCs

    Zhang, H., Matsutani, H., Take, Y., Kuroda, T. & Amano, H., 2012 Feb 28, Architecture of Computing Systems, ARCS 2012 - 25th International Conference, Proceedings. p. 212-224 13 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 7179 LNCS).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    1 Citation (Scopus)
  • 2013

    A case for wireless 3D NoCs for CMPs

    Matsutani, H., Bogdan, P., Marculescu, R., Take, Y., Sasaki, D., Zhang, H., Koibuchi, M., Kuroda, T. & Amano, H., 2013 May 20, 2013 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013. p. 23-28 6 p. 6509553. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    41 Citations (Scopus)
  • A low-power link speed control method on distributed real-time systems

    Kumura, Y., Suito, K., Matsutani, H. & Yamasaki, N., 2013 Jan 1, Proceedings - IEEE 7th International Symposium on Embedded Multicore/Manycore System-on-Chip, MCSoC 2013. IEEE Computer Society, p. 49-54 6 p. 6657903. (Proceedings - IEEE 7th International Symposium on Embedded Multicore/Manycore System-on-Chip, MCSoC 2013).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    1 Citation (Scopus)
  • A routing strategy for inductive-coupling based wireless 3-D NoCs by maximizing topological regularity

    Sasaki, D., Zhang, H., Matsutani, H., Koibuchi, M. & Amano, H., 2013, Algorithms and Architectures for Parallel Processing - 13th International Conference, ICA3PP 2013, Proceedings. PART 2 ed. p. 77-85 9 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 8286 LNCS, no. PART 2).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface

    Miura, N., Koizumi, Y., Sasaki, E., Take, Y., Matsutani, H., Kuroda, T., Amano, H., Sakamoto, R., Namiki, M., Usami, K., Kondo, M. & Nakamura, H., 2013 May 24, 2013 IEEE Hot Chips 25 Symposium, HCS 2013. Institute of Electrical and Electronics Engineers Inc., 7478328. (2013 IEEE Hot Chips 25 Symposium, HCS 2013).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • A scalable 3D heterogeneous multi-core processor with inductive-coupling ThruChip interface

    Miura, N., Koizumi, Y., Sasaki, E., Take, Y., Matsutani, H., Kuroda, T., Amano, H., Sakamoto, R., Namiki, M., Usami, K., Kondo, M. & Nakamura, H., 2013 Aug 15, IEEE Symposium on Low-Power and High-Speed Chips - Proceedings for 2013 COOL Chips XVI. 6547916. (IEEE Symposium on Low-Power and High-Speed Chips - Proceedings for 2013 COOL Chips XVI).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    2 Citations (Scopus)
  • Dynamic power on/off method for 3D NoCs with wireless inductive-coupling links

    Zhang, H., Matsutani, H., Koibuchi, M. & Amano, H., 2013 Aug 15, IEEE Symposium on Low-Power and High-Speed Chips - Proceedings for 2013 COOL Chips XVI. 6547924. (IEEE Symposium on Low-Power and High-Speed Chips - Proceedings for 2013 COOL Chips XVI).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    2 Citations (Scopus)
  • Experimental evaluation of low power techniques on dependable responsive multithreaded processor

    Suito, K., Takasu, M., Ueda, R., Fujii, K., Matsutani, H. & Yamasaki, N., 2013 Sep 5, 28th International Conference on Computers and Their Applications 2013, CATA 2013. p. 281-288 8 p. (28th International Conference on Computers and Their Applications 2013, CATA 2013).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    3 Citations (Scopus)
  • Headfirst sliding routing: A time-based routing scheme for bus-NoC hybrid 3-D architecture

    Kagami, T., Matsutani, H., Koibuchi, M. & Amano, H., 2013, 2013 7th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2013. 6558406. (2013 7th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2013).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    5 Citations (Scopus)
  • Layout-conscious random topologies for HPC off-chip interconnects

    Koibuchi, M., Fujiwara, I., Matsutani, H. & Casanova, H., 2013 Jul 23, 19th IEEE International Symposium on High Performance Computer Architecture, HPCA 2013. p. 484-495 12 p. 6522343. (Proceedings - International Symposium on High-Performance Computer Architecture).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    30 Citations (Scopus)
  • Packet routing for distributed real-time system on real-time communication link

    Yoshizumi, O., Matsutani, H. & Yamasaki, N., 2013, 28th International Conference on Computers and Their Applications 2013, CATA 2013. p. 197-204 8 p. (28th International Conference on Computers and Their Applications 2013, CATA 2013).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • Performance degradation by deactivated cores in 2-D mesh NoCs

    Fujiwara, I., Koibuchi, M. & Matsutani, H., 2013, Proceedings - IEEE 7th International Symposium on Embedded Multicore/Manycore System-on-Chip, MCSoC 2013. IEEE Computer Society, p. 25-30 6 p. 6657899. (Proceedings - IEEE 7th International Symposium on Embedded Multicore/Manycore System-on-Chip, MCSoC 2013).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    1 Citation (Scopus)
  • Research challenges on 2-D and 3-D network-on-chips

    Matsutani, H., 2013 Dec 1, Proceedings - 2013 1st International Symposium on Computing and Networking, CANDAR 2013. p. 24-25 2 p. 6726874. (Proceedings - 2013 1st International Symposium on Computing and Networking, CANDAR 2013).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    2 Citations (Scopus)
  • 2014

    Low-latency wireless 3D NoCs via randomized shortcut chips

    Matsutani, H., Koibuchi, M., Fujiwara, I., Kagami, T., Take, Y., Kuroda, T., Bogdan, P., Marculescu, R. & Amano, H., 2014 Jan 1, Proceedings - Design, Automation and Test in Europe, DATE 2014. Institute of Electrical and Electronics Engineers Inc., 6800487. (Proceedings -Design, Automation and Test in Europe, DATE).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    39 Citations (Scopus)
  • Skywalk: A topology for HPC networks with low-delay switches

    Fujiwara, I., Koibuchi, M., Matsutani, H. & Casanova, H., 2014, Proceedings - IEEE 28th International Parallel and Distributed Processing Symposium, IPDPS 2014. IEEE Computer Society, p. 263-272 10 p. 6877261. (Proceedings of the International Parallel and Distributed Processing Symposium, IPDPS).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    18 Citations (Scopus)
  • 2015

    3D Shared Bus Architecture Using Inductive Coupling Interconnect

    Nomura, A., Fujita, Y., Matsutani, H. & Amano, H., 2015 Nov 11, Proceedings - IEEE 9th International Symposium on Embedded Multicore/Manycore SoCs, MCSoC 2015. Institute of Electrical and Electronics Engineers Inc., p. 259-266 8 p. 7328213

    Research output: Chapter in Book/Report/Conference proceedingConference contribution