Calculated based on number of publications stored in Pure and citations from Scopus
20052022

Research activity per year

If you made any changes in Pure these will be visible here soon.
Filter
Conference contribution

Search results

  • 2009

    Prediction router: Yet another low latency on-chip router architecture

    Matsutani, H., Koibuchi, M., Amano, H. & Yoshinaga, T., 2009, Proceedings - 15th International Symposium on High-Performance Computer Architecture, HPCA - 15 2009. IEEE Computer Society, p. 367-378 12 p. 4798274. (Proceedings - International Symposium on High-Performance Computer Architecture).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    67 Citations (Scopus)
  • 2008

    Adding slow-silent virtual channels for low-power on-chip networks

    Matsutani, H., Koibuchi, M., Wang, D. & Amano, H., 2008, Proceedings - Second IEEE International Symposium on Networks-on-Chip, NOCS 2008. p. 23-32 10 p. 4492722. (Proceedings - Second IEEE International Symposium on Networks-on-Chip, NOCS 2008).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    38 Citations (Scopus)
  • A lightweight fault-tolerant mechanism for network-on-chip

    Koibuchi, M., Matsutani, H., Amano, H. & Pinkston, T. M., 2008 May 28, Proceedings - Second IEEE International Symposium on Networks-on-Chip, NOCS 2008. p. 13-22 10 p. 4492721. (Proceedings - Second IEEE International Symposium on Networks-on-Chip, NOCS 2008).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    116 Citations (Scopus)
  • A link removal methodology for networks-on-chip on reconfigurable systems

    Wang, D., Matsutani, H., Arnano, H. & Koibuchi, M., 2008 Nov 3, Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL. p. 269-274 6 p. 4629943. (Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    10 Citations (Scopus)
  • Run-time power gating of on-chip routers using look-ahead routing

    Matsutani, H., Koibuchi, M., Amano, H. & Wang, D., 2008, 2008 Asia and South Pacific Design Automation Conference, ASP-DAC. p. 55-60 6 p. 4484015. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    75 Citations (Scopus)
  • Three-dimensional layout of on-chip tree-based networks

    Matsutani, H., Koibuchi, M., Hsu, D. F. & Amano, H., 2008, Proceedings - 9th International Symposium on Parallel Architectures, Algorithms and Networks, I-SPAN 2008. p. 281-288 8 p. 4520228. (Proceedings of the International Symposium on Parallel Architectures, Algorithms and Networks, I-SPAN).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    12 Citations (Scopus)
  • 2007

    A temporal correlation based port combination methodology for Networks-on-Chip on reconfigurable systems

    Wang, D., Matsutani, H., Amano, H. & Koibuchi, M., 2007, Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL. p. 383-388 6 p. 4380676. (Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    4 Citations (Scopus)
  • Performance, cost, and energy evaluation of fat H-tree: A cost-efficient tree-based on-chip network

    Matsutani, H., Koibuchi, M. & Amano, H., 2007 Sep 24, Proceedings - 21st International Parallel and Distributed Processing Symposium, IPDPS 2007; Abstracts and CD-ROM. 4227999. (Proceedings - 21st International Parallel and Distributed Processing Symposium, IPDPS 2007; Abstracts and CD-ROM).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    22 Citations (Scopus)
  • Tightly-coupled multi-layer topologies for 3-D NoCs

    Matsutani, H., Koibuchi, M. & Amano, H., 2007, 2007 International Conference on Parallel Processing, ICPP. 4343882. (Proceedings of the International Conference on Parallel Processing).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    68 Citations (Scopus)
  • 2006

    A Virtual-Channel Free Mapping for Application-Specific On-Chip Torus Networks

    Matsutani, H., Koibuchi, M. & Amano, H., 2006, 19th International Conference on Parallel and Distributed Computing Systems 2006, PDCS 2006. International Society for Computers and Their Applications (ISCA), p. 24-31 8 p. (19th International Conference on Parallel and Distributed Computing Systems 2006, PDCS 2006).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    1 Citation (Scopus)
  • Enforcing dimension-order routing in on-chip torus networks without virtual channels

    Matsutani, H., Koibuchi, M. & Amano, H., 2006, Parallel and Distributed Processing and Applications - 4th International Symposium, ISPA 2006, Proceedings. Guo, M., Yang, L. T., Di Martino, B., Zima, H. P., Zima, H. P., Dongarra, J. & Tang, F. (eds.). Springer Verlag, p. 207-218 12 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 4330).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    1 Citation (Scopus)
  • 2005

    An adaptive cryptographic accelerator for IPsec on dynamically reconfigurable processor

    Hasegawa, Y., Abe, S., Matsutani, H., Amano, H., Anjo, K. & Awashima, T., 2005, Proceedings - 2005 IEEE International Conference on Field Programmable Technology. p. 163-170 8 p. 1568541. (Proceedings - 2005 IEEE International Conference on Field Programmable Technology; vol. 2005).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    18 Citations (Scopus)
  • Destination bundle: A routing table reduction technique for distributed routing on dependablenetworks-on-chips

    Matsutani, H., Koibuchi, M. & Amano, H., 2005 Dec 1, Proceedings of the 2005 International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA'05. p. 1343-1349 7 p. (Proceedings of the 2005 International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA'05; vol. 3).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution