∑ΔADC with fractional sample rate conversion for software defined radio receiver

An analog-to-digital converter (∑ΔADC) in a software defined radio (SDR) receiver must be able to support the specifications of various wireless standards. It should also work with the low power supply voltage of CMOS circuits. A ∑ΔADC is one of the solutions for the SDR receiver. However, the power consumption of the circuits, such as a lowpass filter (LPF) and a decimator after the modulator is large due to the high sampling speed. On the other hand, since a different wireless communication standard has a different master clock rate, it is necessary to provide the clock rate suitable for each standard. As a solution for the problem, direct insertion/deletion based sample rate conversion (SRC) has been proposed. Nevertheless, in order to apply this method to the ∑ΔADC, the problem of the high clock speed in the circuits of the LPF after modulator remains. In this paper, a novel ∑ΔADC with fractional SRC is proposed. In the proposed scheme, SRC and filtering are combined. By filtering and decimating the output of the modulator in parallel with Q transversal filters the clock speed of the circuits of the SRC and the LPF can be reduced P times for Q/P SRC.