0.5μm BiCMOS standard-cell macros including 0.5W 3ns register file and 0.6W 5ns 32kB cache

Hiroyuki Hara; Takayasu Sakurai; Tetsu Nagamatsu; Shin'ichi Kobayashi; Katsuhiro Seta; Hiroshi Momose; Yoichirou Niitsu; Hiroyuki Miyakawa; Tadahiro Kuroda; Kouji Matsuda; Yoshinori Watanabe; Fumihiko Sano; Akihiko Chiba

doi:10.1109/ISSCC.1992.200403

0.5μm BiCMOS standard-cell macros including 0.5W 3ns register file and 0.6W 5ns 32kB cache

Hiroyuki Hara, Takayasu Sakurai, Tetsu Nagamatsu, Shin'ichi Kobayashi, Katsuhiro Seta, Hiroshi Momose, Yoichirou Niitsu, Hiroyuki Miyakawa, Tadahiro Kuroda, Kouji Matsuda, Yoshinori Watanabe, Fumihiko Sano, Akihiko Chiba

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Citations (Scopus)

Abstract

BiCMOs standard-cell macros, including a 0.5-W, 3.0-ns register file, a 0.6-W, 5.0-ns 32-kB cache, a 0.2-W, 2.5-ns table look-aside buffer (TLB), and a 0.1-W, 3.0-ns adder, are presented based on a 0.5μm BiCMOs technology. These power consumption values are at 100 MHz operation. Low power and high speed are crucial for high-performance systems requiring a high level of integration. Several BiCMOS/CMOS circuits achieve high-speed operation with a 3.3-V supply. A direct-coupled ECL (emitter-coupled logic)+CMOS circuit is investigated for use as a BiCMOS standard cell.

Original language	English
Title of host publication	Digest Technical Papers - 1992 39th IEEE International Solid-State Circuits Conference, ISSCC 1992
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	46-47
Number of pages	2
ISBN (Electronic)	0780305736
DOIs	https://doi.org/10.1109/ISSCC.1992.200403
Publication status	Published - 1992 Jan 1
Externally published	Yes
Event	39th IEEE International Solid-State Circuits Conference, ISSCC 1992 - San Francisco, United States Duration: 1992 Feb 19 → 1992 Feb 21

Publication series

Name	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume	1992-February
ISSN (Print)	0193-6530

Conference

Conference	39th IEEE International Solid-State Circuits Conference, ISSCC 1992
Country	United States
City	San Francisco
Period	92/2/19 → 92/2/21

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Access to Document

10.1109/ISSCC.1992.200403

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Hara, H., Sakurai, T., Nagamatsu, T., Kobayashi, S., Seta, K., Momose, H., Niitsu, Y., Miyakawa, H., Kuroda, T., Matsuda, K., Watanabe, Y., Sano, F., & Chiba, A. (1992). 0.5μm BiCMOS standard-cell macros including 0.5W 3ns register file and 0.6W 5ns 32kB cache. In Digest Technical Papers - 1992 39th IEEE International Solid-State Circuits Conference, ISSCC 1992 (pp. 46-47). [200403] (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 1992-February). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISSCC.1992.200403

0.5μm BiCMOS standard-cell macros including 0.5W 3ns register file and 0.6W 5ns 32kB cache. / Hara, Hiroyuki; Sakurai, Takayasu; Nagamatsu, Tetsu; Kobayashi, Shin'ichi; Seta, Katsuhiro; Momose, Hiroshi; Niitsu, Yoichirou; Miyakawa, Hiroyuki; Kuroda, Tadahiro; Matsuda, Kouji; Watanabe, Yoshinori; Sano, Fumihiko; Chiba, Akihiko.

Digest Technical Papers - 1992 39th IEEE International Solid-State Circuits Conference, ISSCC 1992. Institute of Electrical and Electronics Engineers Inc., 1992. p. 46-47 200403 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 1992-February).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Hara, H, Sakurai, T, Nagamatsu, T, Kobayashi, S, Seta, K, Momose, H, Niitsu, Y, Miyakawa, H, Kuroda, T, Matsuda, K, Watanabe, Y, Sano, F & Chiba, A 1992, 0.5μm BiCMOS standard-cell macros including 0.5W 3ns register file and 0.6W 5ns 32kB cache. in Digest Technical Papers - 1992 39th IEEE International Solid-State Circuits Conference, ISSCC 1992., 200403, Digest of Technical Papers - IEEE International Solid-State Circuits Conference, vol. 1992-February, Institute of Electrical and Electronics Engineers Inc., pp. 46-47, 39th IEEE International Solid-State Circuits Conference, ISSCC 1992, San Francisco, United States, 92/2/19. https://doi.org/10.1109/ISSCC.1992.200403

Hara H, Sakurai T, Nagamatsu T, Kobayashi S, Seta K, Momose H et al. 0.5μm BiCMOS standard-cell macros including 0.5W 3ns register file and 0.6W 5ns 32kB cache. In Digest Technical Papers - 1992 39th IEEE International Solid-State Circuits Conference, ISSCC 1992. Institute of Electrical and Electronics Engineers Inc. 1992. p. 46-47. 200403. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). https://doi.org/10.1109/ISSCC.1992.200403

Hara, Hiroyuki ; Sakurai, Takayasu ; Nagamatsu, Tetsu ; Kobayashi, Shin'ichi ; Seta, Katsuhiro ; Momose, Hiroshi ; Niitsu, Yoichirou ; Miyakawa, Hiroyuki ; Kuroda, Tadahiro ; Matsuda, Kouji ; Watanabe, Yoshinori ; Sano, Fumihiko ; Chiba, Akihiko. / 0.5μm BiCMOS standard-cell macros including 0.5W 3ns register file and 0.6W 5ns 32kB cache. Digest Technical Papers - 1992 39th IEEE International Solid-State Circuits Conference, ISSCC 1992. Institute of Electrical and Electronics Engineers Inc., 1992. pp. 46-47 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference).

@inproceedings{edd373f5d7d14698ab595ff6b54de2f2,

title = "0.5μm BiCMOS standard-cell macros including 0.5W 3ns register file and 0.6W 5ns 32kB cache",

abstract = "BiCMOs standard-cell macros, including a 0.5-W, 3.0-ns register file, a 0.6-W, 5.0-ns 32-kB cache, a 0.2-W, 2.5-ns table look-aside buffer (TLB), and a 0.1-W, 3.0-ns adder, are presented based on a 0.5μm BiCMOs technology. These power consumption values are at 100 MHz operation. Low power and high speed are crucial for high-performance systems requiring a high level of integration. Several BiCMOS/CMOS circuits achieve high-speed operation with a 3.3-V supply. A direct-coupled ECL (emitter-coupled logic)+CMOS circuit is investigated for use as a BiCMOS standard cell.",

author = "Hiroyuki Hara and Takayasu Sakurai and Tetsu Nagamatsu and Shin'ichi Kobayashi and Katsuhiro Seta and Hiroshi Momose and Yoichirou Niitsu and Hiroyuki Miyakawa and Tadahiro Kuroda and Kouji Matsuda and Yoshinori Watanabe and Fumihiko Sano and Akihiko Chiba",

year = "1992",

month = jan,

day = "1",

doi = "10.1109/ISSCC.1992.200403",

language = "English",

series = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "46--47",

booktitle = "Digest Technical Papers - 1992 39th IEEE International Solid-State Circuits Conference, ISSCC 1992",

note = "39th IEEE International Solid-State Circuits Conference, ISSCC 1992 ; Conference date: 19-02-1992 Through 21-02-1992",

}

TY - GEN

T1 - 0.5μm BiCMOS standard-cell macros including 0.5W 3ns register file and 0.6W 5ns 32kB cache

AU - Hara, Hiroyuki

AU - Sakurai, Takayasu

AU - Nagamatsu, Tetsu

AU - Kobayashi, Shin'ichi

AU - Seta, Katsuhiro

AU - Momose, Hiroshi

AU - Niitsu, Yoichirou

AU - Miyakawa, Hiroyuki

AU - Kuroda, Tadahiro

AU - Matsuda, Kouji

AU - Watanabe, Yoshinori

AU - Sano, Fumihiko

AU - Chiba, Akihiko

PY - 1992/1/1

Y1 - 1992/1/1

N2 - BiCMOs standard-cell macros, including a 0.5-W, 3.0-ns register file, a 0.6-W, 5.0-ns 32-kB cache, a 0.2-W, 2.5-ns table look-aside buffer (TLB), and a 0.1-W, 3.0-ns adder, are presented based on a 0.5μm BiCMOs technology. These power consumption values are at 100 MHz operation. Low power and high speed are crucial for high-performance systems requiring a high level of integration. Several BiCMOS/CMOS circuits achieve high-speed operation with a 3.3-V supply. A direct-coupled ECL (emitter-coupled logic)+CMOS circuit is investigated for use as a BiCMOS standard cell.

AB - BiCMOs standard-cell macros, including a 0.5-W, 3.0-ns register file, a 0.6-W, 5.0-ns 32-kB cache, a 0.2-W, 2.5-ns table look-aside buffer (TLB), and a 0.1-W, 3.0-ns adder, are presented based on a 0.5μm BiCMOs technology. These power consumption values are at 100 MHz operation. Low power and high speed are crucial for high-performance systems requiring a high level of integration. Several BiCMOS/CMOS circuits achieve high-speed operation with a 3.3-V supply. A direct-coupled ECL (emitter-coupled logic)+CMOS circuit is investigated for use as a BiCMOS standard cell.

UR - http://www.scopus.com/inward/record.url?scp=4243193466&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=4243193466&partnerID=8YFLogxK

U2 - 10.1109/ISSCC.1992.200403

DO - 10.1109/ISSCC.1992.200403

M3 - Conference contribution

AN - SCOPUS:4243193466

T3 - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

SP - 46

EP - 47

BT - Digest Technical Papers - 1992 39th IEEE International Solid-State Circuits Conference, ISSCC 1992

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 39th IEEE International Solid-State Circuits Conference, ISSCC 1992

Y2 - 19 February 1992 through 21 February 1992

ER -