Abstract
BiCMOs standard-cell macros, including a 0.5-W, 3.0-ns register file, a 0.6-W, 5.0-ns 32-kB cache, a 0.2-W, 2.5-ns table look-aside buffer (TLB), and a 0.1-W, 3.0-ns adder, are presented based on a 0.5μm BiCMOs technology. These power consumption values are at 100 MHz operation. Low power and high speed are crucial for high-performance systems requiring a high level of integration. Several BiCMOS/CMOS circuits achieve high-speed operation with a 3.3-V supply. A direct-coupled ECL (emitter-coupled logic)+CMOS circuit is investigated for use as a BiCMOS standard cell.
| Original language | English |
|---|---|
| Title of host publication | Digest Technical Papers - 1992 39th IEEE International Solid-State Circuits Conference, ISSCC 1992 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 46-47 |
| Number of pages | 2 |
| ISBN (Electronic) | 0780305736 |
| DOIs | |
| Publication status | Published - 1992 Jan 1 |
| Externally published | Yes |
| Event | 39th IEEE International Solid-State Circuits Conference, ISSCC 1992 - San Francisco, United States Duration: 1992 Feb 19 → 1992 Feb 21 |
Publication series
| Name | Digest of Technical Papers - IEEE International Solid-State Circuits Conference |
|---|---|
| Volume | 1992-February |
| ISSN (Print) | 0193-6530 |
Conference
| Conference | 39th IEEE International Solid-State Circuits Conference, ISSCC 1992 |
|---|---|
| Country | United States |
| City | San Francisco |
| Period | 92/2/19 → 92/2/21 |
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ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering
Cite this
0.5μm BiCMOS standard-cell macros including 0.5W 3ns register file and 0.6W 5ns 32kB cache. / Hara, Hiroyuki; Sakurai, Takayasu; Nagamatsu, Tetsu; Kobayashi, Shin'ichi; Seta, Katsuhiro; Momose, Hiroshi; Niitsu, Yoichirou; Miyakawa, Hiroyuki; Kuroda, Tadahiro; Matsuda, Kouji; Watanabe, Yoshinori; Sano, Fumihiko; Chiba, Akihiko.
Digest Technical Papers - 1992 39th IEEE International Solid-State Circuits Conference, ISSCC 1992. Institute of Electrical and Electronics Engineers Inc., 1992. p. 46-47 200403 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 1992-February).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - 0.5μm BiCMOS standard-cell macros including 0.5W 3ns register file and 0.6W 5ns 32kB cache
AU - Hara, Hiroyuki
AU - Sakurai, Takayasu
AU - Nagamatsu, Tetsu
AU - Kobayashi, Shin'ichi
AU - Seta, Katsuhiro
AU - Momose, Hiroshi
AU - Niitsu, Yoichirou
AU - Miyakawa, Hiroyuki
AU - Kuroda, Tadahiro
AU - Matsuda, Kouji
AU - Watanabe, Yoshinori
AU - Sano, Fumihiko
AU - Chiba, Akihiko
PY - 1992/1/1
Y1 - 1992/1/1
N2 - BiCMOs standard-cell macros, including a 0.5-W, 3.0-ns register file, a 0.6-W, 5.0-ns 32-kB cache, a 0.2-W, 2.5-ns table look-aside buffer (TLB), and a 0.1-W, 3.0-ns adder, are presented based on a 0.5μm BiCMOs technology. These power consumption values are at 100 MHz operation. Low power and high speed are crucial for high-performance systems requiring a high level of integration. Several BiCMOS/CMOS circuits achieve high-speed operation with a 3.3-V supply. A direct-coupled ECL (emitter-coupled logic)+CMOS circuit is investigated for use as a BiCMOS standard cell.
AB - BiCMOs standard-cell macros, including a 0.5-W, 3.0-ns register file, a 0.6-W, 5.0-ns 32-kB cache, a 0.2-W, 2.5-ns table look-aside buffer (TLB), and a 0.1-W, 3.0-ns adder, are presented based on a 0.5μm BiCMOs technology. These power consumption values are at 100 MHz operation. Low power and high speed are crucial for high-performance systems requiring a high level of integration. Several BiCMOS/CMOS circuits achieve high-speed operation with a 3.3-V supply. A direct-coupled ECL (emitter-coupled logic)+CMOS circuit is investigated for use as a BiCMOS standard cell.
UR - http://www.scopus.com/inward/record.url?scp=4243193466&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=4243193466&partnerID=8YFLogxK
U2 - 10.1109/ISSCC.1992.200403
DO - 10.1109/ISSCC.1992.200403
M3 - Conference contribution
AN - SCOPUS:4243193466
T3 - Digest of Technical Papers - IEEE International Solid-State Circuits Conference
SP - 46
EP - 47
BT - Digest Technical Papers - 1992 39th IEEE International Solid-State Circuits Conference, ISSCC 1992
PB - Institute of Electrical and Electronics Engineers Inc.
ER -