0.5μm BiCMOS standard-cell macros including 0.5W 3ns register file and 0.6W 5ns 32kB cache

Hiroyuki Hara, Takayasu Sakurai, Tetsu Nagamatsu, Shin'ichi Kobayashi, Katsuhiro Seta, Hiroshi Momose, Yoichirou Niitsu, Hiroyuki Miyakawa, Tadahiro Kuroda, Kouji Matsuda, Yoshinori Watanabe, Fumihiko Sano, Akihiko Chiba

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

BiCMOs standard-cell macros, including a 0.5-W, 3.0-ns register file, a 0.6-W, 5.0-ns 32-kB cache, a 0.2-W, 2.5-ns table look-aside buffer (TLB), and a 0.1-W, 3.0-ns adder, are presented based on a 0.5μm BiCMOs technology. These power consumption values are at 100 MHz operation. Low power and high speed are crucial for high-performance systems requiring a high level of integration. Several BiCMOS/CMOS circuits achieve high-speed operation with a 3.3-V supply. A direct-coupled ECL (emitter-coupled logic)+CMOS circuit is investigated for use as a BiCMOS standard cell.

Original languageEnglish
Title of host publicationDigest Technical Papers - 1992 39th IEEE International Solid-State Circuits Conference, ISSCC 1992
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages46-47
Number of pages2
ISBN (Electronic)0780305736
DOIs
Publication statusPublished - 1992 Jan 1
Externally publishedYes
Event39th IEEE International Solid-State Circuits Conference, ISSCC 1992 - San Francisco, United States
Duration: 1992 Feb 191992 Feb 21

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume1992-February
ISSN (Print)0193-6530

Conference

Conference39th IEEE International Solid-State Circuits Conference, ISSCC 1992
CountryUnited States
CitySan Francisco
Period92/2/1992/2/21

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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    Hara, H., Sakurai, T., Nagamatsu, T., Kobayashi, S., Seta, K., Momose, H., Niitsu, Y., Miyakawa, H., Kuroda, T., Matsuda, K., Watanabe, Y., Sano, F., & Chiba, A. (1992). 0.5μm BiCMOS standard-cell macros including 0.5W 3ns register file and 0.6W 5ns 32kB cache. In Digest Technical Papers - 1992 39th IEEE International Solid-State Circuits Conference, ISSCC 1992 (pp. 46-47). [200403] (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 1992-February). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISSCC.1992.200403