Abstract
Presented is a two-dimensional 8×8 discrete cosine transform (DCT) core processor for portable multimedia equipment with HDTV resolution in a 0.3μm CMOS triple-well double-metal technology which operates at 150MHz from a 0.9V power supply and consumes 10mW, only 2% power dissipation of a previous 3.3V DCT. Circuit techniques for dynamically varying threshold voltage reduce active power dissipation with negligible overhead in speed standby power and chip area.
| Original language | English |
|---|---|
| Title of host publication | Digest of Technical Papers - IEEE International Solid-State Circuits Conference |
| Publisher | IEEE |
| Pages | 166-167 |
| Number of pages | 2 |
| Volume | 39 |
| Publication status | Published - 1996 Feb |
| Externally published | Yes |
| Event | Proceedings of the 1996 IEEE International Solid-State Circuits Conference - San Francisco, CA, USA Duration: 1996 Feb 8 → 1996 Feb 10 |
Other
| Other | Proceedings of the 1996 IEEE International Solid-State Circuits Conference |
|---|---|
| City | San Francisco, CA, USA |
| Period | 96/2/8 → 96/2/10 |
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ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering
Cite this
0.9V 150MHz 10mW 4mm2 2-D discrete cosine transform core processor with variable-threshold-voltage scheme. / Kuroda, Tadahiro; Fujita, Tetsuya; Mita, Shinji; Nagamatu, Tetsu; Yoshioka, Shinichi; Sano, Fumihiko; Norishima, Masayuki; Murota, Masayuki; Kako, Makoto; Kinugawa, Masaaki; Kakumu, Masakazu; Sakurai, Takayasu.
Digest of Technical Papers - IEEE International Solid-State Circuits Conference. Vol. 39 IEEE, 1996. p. 166-167.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - 0.9V 150MHz 10mW 4mm2 2-D discrete cosine transform core processor with variable-threshold-voltage scheme
AU - Kuroda, Tadahiro
AU - Fujita, Tetsuya
AU - Mita, Shinji
AU - Nagamatu, Tetsu
AU - Yoshioka, Shinichi
AU - Sano, Fumihiko
AU - Norishima, Masayuki
AU - Murota, Masayuki
AU - Kako, Makoto
AU - Kinugawa, Masaaki
AU - Kakumu, Masakazu
AU - Sakurai, Takayasu
PY - 1996/2
Y1 - 1996/2
N2 - Presented is a two-dimensional 8×8 discrete cosine transform (DCT) core processor for portable multimedia equipment with HDTV resolution in a 0.3μm CMOS triple-well double-metal technology which operates at 150MHz from a 0.9V power supply and consumes 10mW, only 2% power dissipation of a previous 3.3V DCT. Circuit techniques for dynamically varying threshold voltage reduce active power dissipation with negligible overhead in speed standby power and chip area.
AB - Presented is a two-dimensional 8×8 discrete cosine transform (DCT) core processor for portable multimedia equipment with HDTV resolution in a 0.3μm CMOS triple-well double-metal technology which operates at 150MHz from a 0.9V power supply and consumes 10mW, only 2% power dissipation of a previous 3.3V DCT. Circuit techniques for dynamically varying threshold voltage reduce active power dissipation with negligible overhead in speed standby power and chip area.
UR - http://www.scopus.com/inward/record.url?scp=0030086605&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0030086605&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:0030086605
VL - 39
SP - 166
EP - 167
BT - Digest of Technical Papers - IEEE International Solid-State Circuits Conference
PB - IEEE
ER -