0.9V 150MHz 10mW 4mm2 2-D discrete cosine transform core processor with variable-threshold-voltage scheme

Tadahiro Kuroda; Tetsuya Fujita; Shinji Mita; Tetsu Nagamatu; Shinichi Yoshioka; Fumihiko Sano; Masayuki Norishima; Masayuki Murota; Makoto Kako; Masaaki Kinugawa; Masakazu Kakumu; Takayasu Sakurai

0.9V 150MHz 10mW 4mm² 2-D discrete cosine transform core processor with variable-threshold-voltage scheme

Tadahiro Kuroda, Tetsuya Fujita, Shinji Mita, Tetsu Nagamatu, Shinichi Yoshioka, Fumihiko Sano, Masayuki Norishima, Masayuki Murota, Makoto Kako, Masaaki Kinugawa, Masakazu Kakumu, Takayasu Sakurai

Research output: Contribution to journal › Conference article › peer-review

110 Citations (Scopus)

Abstract

Presented is a two-dimensional 8×8 discrete cosine transform (DCT) core processor for portable multimedia equipment with HDTV resolution in a 0.3μm CMOS triple-well double-metal technology which operates at 150MHz from a 0.9V power supply and consumes 10mW, only 2% power dissipation of a previous 3.3V DCT. Circuit techniques for dynamically varying threshold voltage reduce active power dissipation with negligible overhead in speed standby power and chip area.

Original language	English
Pages (from-to)	166-167
Number of pages	2
Journal	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume	39
Publication status	Published - 1996 Feb 1
Externally published	Yes
Event	Proceedings of the 1996 IEEE International Solid-State Circuits Conference - San Francisco, CA, USA Duration: 1996 Feb 8 → 1996 Feb 10

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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0.9V 150MHz 10mW 4mm² 2-D discrete cosine transform core processor with variable-threshold-voltage scheme. / Kuroda, Tadahiro; Fujita, Tetsuya; Mita, Shinji; Nagamatu, Tetsu; Yoshioka, Shinichi; Sano, Fumihiko; Norishima, Masayuki; Murota, Masayuki; Kako, Makoto; Kinugawa, Masaaki; Kakumu, Masakazu; Sakurai, Takayasu.

In: Digest of Technical Papers - IEEE International Solid-State Circuits Conference, Vol. 39, 01.02.1996, p. 166-167.

Research output: Contribution to journal › Conference article › peer-review

Kuroda, Tadahiro ; Fujita, Tetsuya ; Mita, Shinji ; Nagamatu, Tetsu ; Yoshioka, Shinichi ; Sano, Fumihiko ; Norishima, Masayuki ; Murota, Masayuki ; Kako, Makoto ; Kinugawa, Masaaki ; Kakumu, Masakazu ; Sakurai, Takayasu. / 0.9V 150MHz 10mW 4mm² 2-D discrete cosine transform core processor with variable-threshold-voltage scheme. In: Digest of Technical Papers - IEEE International Solid-State Circuits Conference. 1996 ; Vol. 39. pp. 166-167.

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AU - Kuroda, Tadahiro

AU - Fujita, Tetsuya

AU - Mita, Shinji

AU - Nagamatu, Tetsu

AU - Yoshioka, Shinichi

AU - Sano, Fumihiko

AU - Norishima, Masayuki

AU - Murota, Masayuki

AU - Kako, Makoto

AU - Kinugawa, Masaaki

AU - Kakumu, Masakazu

AU - Sakurai, Takayasu

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AB - Presented is a two-dimensional 8×8 discrete cosine transform (DCT) core processor for portable multimedia equipment with HDTV resolution in a 0.3μm CMOS triple-well double-metal technology which operates at 150MHz from a 0.9V power supply and consumes 10mW, only 2% power dissipation of a previous 3.3V DCT. Circuit techniques for dynamically varying threshold voltage reduce active power dissipation with negligible overhead in speed standby power and chip area.

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0.9V 150MHz 10mW 4mm² 2-D discrete cosine transform core processor with variable-threshold-voltage scheme

Abstract

ASJC Scopus subject areas

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