0.9V 150MHz 10mW 4mm2 2-D discrete cosine transform core processor with variable-threshold-voltage scheme

Tadahiro Kuroda, Tetsuya Fujita, Shinji Mita, Tetsu Nagamatu, Shinichi Yoshioka, Fumihiko Sano, Masayuki Norishima, Masayuki Murota, Makoto Kako, Masaaki Kinugawa, Masakazu Kakumu, Takayasu Sakurai

Research output: Contribution to journalConference article

103 Citations (Scopus)

Abstract

Presented is a two-dimensional 8×8 discrete cosine transform (DCT) core processor for portable multimedia equipment with HDTV resolution in a 0.3μm CMOS triple-well double-metal technology which operates at 150MHz from a 0.9V power supply and consumes 10mW, only 2% power dissipation of a previous 3.3V DCT. Circuit techniques for dynamically varying threshold voltage reduce active power dissipation with negligible overhead in speed standby power and chip area.

Original languageEnglish
Pages (from-to)166-167
Number of pages2
JournalDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume39
Publication statusPublished - 1996 Feb 1
Externally publishedYes
EventProceedings of the 1996 IEEE International Solid-State Circuits Conference - San Francisco, CA, USA
Duration: 1996 Feb 81996 Feb 10

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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    Kuroda, T., Fujita, T., Mita, S., Nagamatu, T., Yoshioka, S., Sano, F., Norishima, M., Murota, M., Kako, M., Kinugawa, M., Kakumu, M., & Sakurai, T. (1996). 0.9V 150MHz 10mW 4mm2 2-D discrete cosine transform core processor with variable-threshold-voltage scheme. Digest of Technical Papers - IEEE International Solid-State Circuits Conference, 39, 166-167.