0.9V 150MHz 10mW 4mm2 2-D discrete cosine transform core processor with variable-threshold-voltage scheme

Tadahiro Kuroda; Tetsuya Fujita; Shinji Mita; Tetsu Nagamatu; Shinichi Yoshioka; Fumihiko Sano; Masayuki Norishima; Masayuki Murota; Makoto Kako; Masaaki Kinugawa; Masakazu Kakumu; Takayasu Sakurai

0.9V 150MHz 10mW 4mm² 2-D discrete cosine transform core processor with variable-threshold-voltage scheme

Tadahiro Kuroda, Tetsuya Fujita, Shinji Mita, Tetsu Nagamatu, Shinichi Yoshioka, Fumihiko Sano, Masayuki Norishima, Masayuki Murota, Makoto Kako, Masaaki Kinugawa, Masakazu Kakumu, Takayasu Sakurai

Research output: Contribution to journal › Conference article › peer-review

110 Citations (Scopus)

Abstract

Presented is a two-dimensional 8×8 discrete cosine transform (DCT) core processor for portable multimedia equipment with HDTV resolution in a 0.3μm CMOS triple-well double-metal technology which operates at 150MHz from a 0.9V power supply and consumes 10mW, only 2% power dissipation of a previous 3.3V DCT. Circuit techniques for dynamically varying threshold voltage reduce active power dissipation with negligible overhead in speed standby power and chip area.

Original language	English
Pages (from-to)	166-167
Number of pages	2
Journal	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume	39
Publication status	Published - 1996 Feb 1
Externally published	Yes
Event	Proceedings of the 1996 IEEE International Solid-State Circuits Conference - San Francisco, CA, USA Duration: 1996 Feb 8 → 1996 Feb 10

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Cite this

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title = "0.9V 150MHz 10mW 4mm2 2-D discrete cosine transform core processor with variable-threshold-voltage scheme",

abstract = "Presented is a two-dimensional 8×8 discrete cosine transform (DCT) core processor for portable multimedia equipment with HDTV resolution in a 0.3μm CMOS triple-well double-metal technology which operates at 150MHz from a 0.9V power supply and consumes 10mW, only 2% power dissipation of a previous 3.3V DCT. Circuit techniques for dynamically varying threshold voltage reduce active power dissipation with negligible overhead in speed standby power and chip area.",

author = "Tadahiro Kuroda and Tetsuya Fujita and Shinji Mita and Tetsu Nagamatu and Shinichi Yoshioka and Fumihiko Sano and Masayuki Norishima and Masayuki Murota and Makoto Kako and Masaaki Kinugawa and Masakazu Kakumu and Takayasu Sakurai",

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journal = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",

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note = "Proceedings of the 1996 IEEE International Solid-State Circuits Conference ; Conference date: 08-02-1996 Through 10-02-1996",

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TY - JOUR

T1 - 0.9V 150MHz 10mW 4mm2 2-D discrete cosine transform core processor with variable-threshold-voltage scheme

AU - Kuroda, Tadahiro

AU - Fujita, Tetsuya

AU - Mita, Shinji

AU - Nagamatu, Tetsu

AU - Yoshioka, Shinichi

AU - Sano, Fumihiko

AU - Norishima, Masayuki

AU - Murota, Masayuki

AU - Kako, Makoto

AU - Kinugawa, Masaaki

AU - Kakumu, Masakazu

AU - Sakurai, Takayasu

PY - 1996/2/1

Y1 - 1996/2/1

N2 - Presented is a two-dimensional 8×8 discrete cosine transform (DCT) core processor for portable multimedia equipment with HDTV resolution in a 0.3μm CMOS triple-well double-metal technology which operates at 150MHz from a 0.9V power supply and consumes 10mW, only 2% power dissipation of a previous 3.3V DCT. Circuit techniques for dynamically varying threshold voltage reduce active power dissipation with negligible overhead in speed standby power and chip area.

AB - Presented is a two-dimensional 8×8 discrete cosine transform (DCT) core processor for portable multimedia equipment with HDTV resolution in a 0.3μm CMOS triple-well double-metal technology which operates at 150MHz from a 0.9V power supply and consumes 10mW, only 2% power dissipation of a previous 3.3V DCT. Circuit techniques for dynamically varying threshold voltage reduce active power dissipation with negligible overhead in speed standby power and chip area.

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M3 - Conference article

AN - SCOPUS:0030086605

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EP - 167

JO - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

JF - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

SN - 0193-6530

T2 - Proceedings of the 1996 IEEE International Solid-State Circuits Conference

Y2 - 8 February 1996 through 10 February 1996

ER -

0.9V 150MHz 10mW 4mm² 2-D discrete cosine transform core processor with variable-threshold-voltage scheme

Abstract

ASJC Scopus subject areas

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