0.9V 150MHz 10mW 4mm2 2-D discrete cosine transform core processor with variable-threshold-voltage scheme

Tadahiro Kuroda, Tetsuya Fujita, Shinji Mita, Tetsu Nagamatu, Shinichi Yoshioka, Fumihiko Sano, Masayuki Norishima, Masayuki Murota, Makoto Kako, Masaaki Kinugawa, Masakazu Kakumu, Takayasu Sakurai

Research output: Chapter in Book/Report/Conference proceedingConference contribution

102 Citations (Scopus)

Abstract

Presented is a two-dimensional 8×8 discrete cosine transform (DCT) core processor for portable multimedia equipment with HDTV resolution in a 0.3μm CMOS triple-well double-metal technology which operates at 150MHz from a 0.9V power supply and consumes 10mW, only 2% power dissipation of a previous 3.3V DCT. Circuit techniques for dynamically varying threshold voltage reduce active power dissipation with negligible overhead in speed standby power and chip area.

Original languageEnglish
Title of host publicationDigest of Technical Papers - IEEE International Solid-State Circuits Conference
PublisherIEEE
Pages166-167
Number of pages2
Volume39
Publication statusPublished - 1996 Feb
Externally publishedYes
EventProceedings of the 1996 IEEE International Solid-State Circuits Conference - San Francisco, CA, USA
Duration: 1996 Feb 81996 Feb 10

Other

OtherProceedings of the 1996 IEEE International Solid-State Circuits Conference
CitySan Francisco, CA, USA
Period96/2/896/2/10

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ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Kuroda, T., Fujita, T., Mita, S., Nagamatu, T., Yoshioka, S., Sano, F., ... Sakurai, T. (1996). 0.9V 150MHz 10mW 4mm2 2-D discrete cosine transform core processor with variable-threshold-voltage scheme. In Digest of Technical Papers - IEEE International Solid-State Circuits Conference (Vol. 39, pp. 166-167). IEEE.