100-Gb/s Physical-layer architecture for next-generation ethernet

Hidehiro Toyoda, Shinji Nishimura, Michitaka Okuno, Kouji Fukuda, Kouji Nakahara, Hiroaki Nishi

Research output: Contribution to journalArticle

11 Citations (Scopus)

Abstract

A high-speed physical-layer architecture for Ethernet is described that supports 100-Gb/s throughput and 40-km transmission, making it well suited for next-generation metro-area and intrabuilding networks. Its links comprise 12 × 10-Gb/s synchronized parallel optical lanes. Ethernet data frames are transmitted by coarse wavelength division multiplexing link and bundled optical fibers. Ten of the lanes convey 640-bit data synchronously (64 bits × 10 lanes). One conveys forward error correction code ((132 b, 140 b) Hamming code), providing highly reliable (BER < 10-12) data transmission, and the other conveys parity data, enabling fault-lane recovery. A newly developed 64B/66B code-sequence-based deskewing mechanism is used that provides low-latency compensation for the lane-to-lane skew, which is less than 88 ns. Testing of this physical-layer architecture in a field programmable gate array circuit demonstrated that it can provide 100-Gb/s data communication with a 590 k gate circuit, which is small enough for implementation in a single LSI circuit.

Original languageEnglish
Pages (from-to)696-702
Number of pages7
JournalIEICE Transactions on Communications
VolumeE89-B
Issue number3
DOIs
Publication statusPublished - 2006 Jan 1

Keywords

  • Ethernet
  • FEC
  • MAN
  • Skew

ASJC Scopus subject areas

  • Software
  • Computer Networks and Communications
  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of '100-Gb/s Physical-layer architecture for next-generation ethernet'. Together they form a unique fingerprint.

  • Cite this