TY - GEN
T1 - 10nm-diameter tri-gate silicon nanowire MOSFETs with enhanced high-field transport and V th tunability through thin BOX
AU - Saitoh, Masumi
AU - Ota, Kensuke
AU - Tanaka, Chika
AU - Uchida, Ken
AU - Numata, Toshinori
PY - 2012
Y1 - 2012
N2 - We demonstrate high-performance 10nm-diameter tri-gate nanowire transistors (NW Tr.) with V th tunability, small variability and negligible self-heating. Optimized S/D and stress memorization technique (SMT) lead to significant parasitic resistance reduction and mobility enhancement. Saturation velocity increase by SMT further enhances high-field carrier velocity and I on of 1mA/μm at I off of 100nA/μm is achieved. We also demonstrate V th control in tri-gate NW Tr. with thin BOX for the first time. The degradation of body effect by NW narrowing can be recovered by thinning NW height, enabling dynamic power and performance management.
AB - We demonstrate high-performance 10nm-diameter tri-gate nanowire transistors (NW Tr.) with V th tunability, small variability and negligible self-heating. Optimized S/D and stress memorization technique (SMT) lead to significant parasitic resistance reduction and mobility enhancement. Saturation velocity increase by SMT further enhances high-field carrier velocity and I on of 1mA/μm at I off of 100nA/μm is achieved. We also demonstrate V th control in tri-gate NW Tr. with thin BOX for the first time. The degradation of body effect by NW narrowing can be recovered by thinning NW height, enabling dynamic power and performance management.
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U2 - 10.1109/VLSIT.2012.6242436
DO - 10.1109/VLSIT.2012.6242436
M3 - Conference contribution
AN - SCOPUS:84866555040
SN - 9781467308458
T3 - Digest of Technical Papers - Symposium on VLSI Technology
SP - 11
EP - 12
BT - 2012 Symposium on VLSI Technology, VLSIT 2012 - Digest of Technical Papers
T2 - 2012 Symposium on VLSI Technology, VLSIT 2012
Y2 - 12 June 2012 through 14 June 2012
ER -