A low-power high-speed chip-to-chip interface scheme is described having a density of 625pins/mm2. The interface utilizes capacitively coupled contactless minipads, return-to-half-VDD signaling and sense amplifying F/F. The measured test chip fabricated in 0.35μm CMOS delivers up to 1.27Gb/s/pin at 3mW/pin.
|Journal||Digest of Technical Papers - IEEE International Solid-State Circuits Conference|
|Publication status||Published - 2003|
|Event||2003 Digest of Technical Papers - , United States|
Duration: 2003 Feb 9 → 2003 Feb 13
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering