1.27Gb/s/pin 3mW/pin wireless superconnect (WSC) interface scheme

Kouichi Kanda; Danardono Dwi Antono; Koichi Ishida; Hiroshi Kawaguchi; Tadahiro Kuroda; Takayasu Sakurai

1.27Gb/s/pin 3mW/pin wireless superconnect (WSC) interface scheme

Kouichi Kanda, Danardono Dwi Antono, Koichi Ishida, Hiroshi Kawaguchi, Tadahiro Kuroda, Takayasu Sakurai

Research output: Contribution to journal › Conference article

Abstract

A low-power high-speed chip-to-chip interface scheme is described having a density of 625pins/mm². The interface utilizes capacitively coupled contactless minipads, return-to-half-V_DD signaling and sense amplifying F/F. The measured test chip fabricated in 0.35μm CMOS delivers up to 1.27Gb/s/pin at 3mW/pin.

Original language	English
Pages (from-to)	173+186-187+487
Journal	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Publication status	Published - 2003 Jul 23
Event	2003 Digest of Technical Papers - , United States Duration: 2003 Feb 9 → 2003 Feb 13

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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Cite this

Kanda, K., Dwi Antono, D., Ishida, K., Kawaguchi, H., Kuroda, T., & Sakurai, T. (2003). 1.27Gb/s/pin 3mW/pin wireless superconnect (WSC) interface scheme. Digest of Technical Papers - IEEE International Solid-State Circuits Conference, 173+186-187+487.

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abstract = "A low-power high-speed chip-to-chip interface scheme is described having a density of 625pins/mm2. The interface utilizes capacitively coupled contactless minipads, return-to-half-VDD signaling and sense amplifying F/F. The measured test chip fabricated in 0.35μm CMOS delivers up to 1.27Gb/s/pin at 3mW/pin.",

author = "Kouichi Kanda and {Dwi Antono}, Danardono and Koichi Ishida and Hiroshi Kawaguchi and Tadahiro Kuroda and Takayasu Sakurai",

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AU - Kanda, Kouichi

AU - Dwi Antono, Danardono

AU - Ishida, Koichi

AU - Kawaguchi, Hiroshi

AU - Kuroda, Tadahiro

AU - Sakurai, Takayasu

PY - 2003/7/23

Y1 - 2003/7/23

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AB - A low-power high-speed chip-to-chip interface scheme is described having a density of 625pins/mm2. The interface utilizes capacitively coupled contactless minipads, return-to-half-VDD signaling and sense amplifying F/F. The measured test chip fabricated in 0.35μm CMOS delivers up to 1.27Gb/s/pin at 3mW/pin.

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AN - SCOPUS:0038306477

SP - 173+186-187+487

JO - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

JF - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

SN - 0193-6530

T2 - 2003 Digest of Technical Papers

Y2 - 9 February 2003 through 13 February 2003

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