Abstract
A low-power high-speed chip-to-chip interface scheme is described having a density of 625pins/mm2. The interface utilizes capacitively coupled contactless minipads, return-to-half-VDD signaling and sense amplifying F/F. The measured test chip fabricated in 0.35μm CMOS delivers up to 1.27Gb/s/pin at 3mW/pin.
| Original language | English |
|---|---|
| Title of host publication | Digest of Technical Papers - IEEE International Solid-State Circuits Conference |
| Editors | L.C. Fujino, A. Grabel, D. Jeager, K.C. Smith |
| Publication status | Published - 2003 |
| Event | 2003 Digest of Technical Papers - , United States Duration: 2003 Feb 9 → 2003 Feb 13 |
Other
| Other | 2003 Digest of Technical Papers |
|---|---|
| Country | United States |
| Period | 03/2/9 → 03/2/13 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Hardware and Architecture
Cite this
1.27Gb/s/pin 3mW/pin wireless superconnect (WSC) interface scheme. / Kanda, Kouichi; Dwi Antono, Danardono; Ishida, Koichi; Kawaguchi, Hiroshi; Kuroda, Tadahiro; Sakurai, Takayasu.
Digest of Technical Papers - IEEE International Solid-State Circuits Conference. ed. / L.C. Fujino; A. Grabel; D. Jeager; K.C. Smith. 2003.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - 1.27Gb/s/pin 3mW/pin wireless superconnect (WSC) interface scheme
AU - Kanda, Kouichi
AU - Dwi Antono, Danardono
AU - Ishida, Koichi
AU - Kawaguchi, Hiroshi
AU - Kuroda, Tadahiro
AU - Sakurai, Takayasu
PY - 2003
Y1 - 2003
N2 - A low-power high-speed chip-to-chip interface scheme is described having a density of 625pins/mm2. The interface utilizes capacitively coupled contactless minipads, return-to-half-VDD signaling and sense amplifying F/F. The measured test chip fabricated in 0.35μm CMOS delivers up to 1.27Gb/s/pin at 3mW/pin.
AB - A low-power high-speed chip-to-chip interface scheme is described having a density of 625pins/mm2. The interface utilizes capacitively coupled contactless minipads, return-to-half-VDD signaling and sense amplifying F/F. The measured test chip fabricated in 0.35μm CMOS delivers up to 1.27Gb/s/pin at 3mW/pin.
UR - http://www.scopus.com/inward/record.url?scp=0038306477&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0038306477&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:0038306477
BT - Digest of Technical Papers - IEEE International Solid-State Circuits Conference
A2 - Fujino, L.C.
A2 - Grabel, A.
A2 - Jeager, D.
A2 - Smith, K.C.
ER -