1.27Gb/s/pin 3mW/pin wireless superconnect (WSC) interface scheme

Kouichi Kanda, Danardono Dwi Antono, Koichi Ishida, Hiroshi Kawaguchi, Tadahiro Kuroda, Takayasu Sakurai

Research output: Chapter in Book/Report/Conference proceedingConference contribution

100 Citations (Scopus)

Abstract

A low-power high-speed chip-to-chip interface scheme is described having a density of 625pins/mm2. The interface utilizes capacitively coupled contactless minipads, return-to-half-VDD signaling and sense amplifying F/F. The measured test chip fabricated in 0.35μm CMOS delivers up to 1.27Gb/s/pin at 3mW/pin.

Original languageEnglish
Title of host publicationDigest of Technical Papers - IEEE International Solid-State Circuits Conference
EditorsL.C. Fujino, A. Grabel, D. Jeager, K.C. Smith
Publication statusPublished - 2003
Event2003 Digest of Technical Papers - , United States
Duration: 2003 Feb 92003 Feb 13

Other

Other2003 Digest of Technical Papers
CountryUnited States
Period03/2/903/2/13

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture

Cite this

Kanda, K., Dwi Antono, D., Ishida, K., Kawaguchi, H., Kuroda, T., & Sakurai, T. (2003). 1.27Gb/s/pin 3mW/pin wireless superconnect (WSC) interface scheme. In L. C. Fujino, A. Grabel, D. Jeager, & K. C. Smith (Eds.), Digest of Technical Papers - IEEE International Solid-State Circuits Conference