1.65 Gb/s 60 mW 4: 1 multiplexer and 1.8 Gb/s 80 mW 1:4 demultiplexer ICs using 2 V 3-level series-gating ECL circuits

Tadahiro Kuroda, Tetsuya Fujita, Yasushi Itabashi, Satohiko Kabumoto, Makoto Noda, Akira Kanuma

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Abstract

The 1.65 Gb/s 60 mW 4:1 multiplexer and 1.8 Gb/s 80 mW 1:4 demultiplexer ICs in a 1.2 μm, 15 GHz bipolar process operate with a -2 V single power supply and exhibit the lowest power-delay products reported to date. Low dissipation results from ECL circuit techniques enabling three-level series gating with a 2 V supply. Gate stacking in ECL is effective in reducing power dissipation because complex logic can be implemented in a single gate with fewer current sources.

Original languageEnglish
Title of host publicationDigest of Technical Papers - IEEE International Solid-State Circuits Conference
PublisherIEEE
Volume38
Publication statusPublished - 1995 Feb
Externally publishedYes
EventProceedings of the 1995 IEEE International Solid-State Circuits Conference - San Francisco, CA, USA
Duration: 1995 Feb 151995 Feb 17

Other

OtherProceedings of the 1995 IEEE International Solid-State Circuits Conference
CitySan Francisco, CA, USA
Period95/2/1595/2/17

Fingerprint

Emitter coupled logic circuits
Networks (circuits)
Energy dissipation

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Kuroda, T., Fujita, T., Itabashi, Y., Kabumoto, S., Noda, M., & Kanuma, A. (1995). 1.65 Gb/s 60 mW 4: 1 multiplexer and 1.8 Gb/s 80 mW 1:4 demultiplexer ICs using 2 V 3-level series-gating ECL circuits. In Digest of Technical Papers - IEEE International Solid-State Circuits Conference (Vol. 38). IEEE.

1.65 Gb/s 60 mW 4 : 1 multiplexer and 1.8 Gb/s 80 mW 1:4 demultiplexer ICs using 2 V 3-level series-gating ECL circuits. / Kuroda, Tadahiro; Fujita, Tetsuya; Itabashi, Yasushi; Kabumoto, Satohiko; Noda, Makoto; Kanuma, Akira.

Digest of Technical Papers - IEEE International Solid-State Circuits Conference. Vol. 38 IEEE, 1995.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Kuroda, T, Fujita, T, Itabashi, Y, Kabumoto, S, Noda, M & Kanuma, A 1995, 1.65 Gb/s 60 mW 4: 1 multiplexer and 1.8 Gb/s 80 mW 1:4 demultiplexer ICs using 2 V 3-level series-gating ECL circuits. in Digest of Technical Papers - IEEE International Solid-State Circuits Conference. vol. 38, IEEE, Proceedings of the 1995 IEEE International Solid-State Circuits Conference, San Francisco, CA, USA, 95/2/15.
Kuroda T, Fujita T, Itabashi Y, Kabumoto S, Noda M, Kanuma A. 1.65 Gb/s 60 mW 4: 1 multiplexer and 1.8 Gb/s 80 mW 1:4 demultiplexer ICs using 2 V 3-level series-gating ECL circuits. In Digest of Technical Papers - IEEE International Solid-State Circuits Conference. Vol. 38. IEEE. 1995
Kuroda, Tadahiro ; Fujita, Tetsuya ; Itabashi, Yasushi ; Kabumoto, Satohiko ; Noda, Makoto ; Kanuma, Akira. / 1.65 Gb/s 60 mW 4 : 1 multiplexer and 1.8 Gb/s 80 mW 1:4 demultiplexer ICs using 2 V 3-level series-gating ECL circuits. Digest of Technical Papers - IEEE International Solid-State Circuits Conference. Vol. 38 IEEE, 1995.
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