1.65 Gb/s 60 mW 4:1 multiplexer and 1.8 Gb/s 80 mW 1:4 demultiplexer ICs using 2 V 3-level series-gating ECL circuits

Tadahiro Kuroda, Tetsuya Fujita, Yasushi Itabashi, Satohiko Kabumoto, Makoto Noda, Akira Kanuma

Research output: Contribution to journalConference article

7 Citations (Scopus)

Abstract

The 1.65 Gb/s 60 mW 4:1 multiplexer and 1.8 Gb/s 80 mW 1:4 demultiplexer ICs in a 1.2 μm, 15 GHz bipolar process operate with a -2 V single power supply and exhibit the lowest power-delay products reported to date. Low dissipation results from ECL circuit techniques enabling three-level series gating with a 2 V supply. Gate stacking in ECL is effective in reducing power dissipation because complex logic can be implemented in a single gate with fewer current sources.

Original languageEnglish
JournalDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume38
Publication statusPublished - 1995 Feb 1
Externally publishedYes
EventProceedings of the 1995 IEEE International Solid-State Circuits Conference - San Francisco, CA, USA
Duration: 1995 Feb 151995 Feb 17

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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