18-GHz clock distribution using a coupled VCO array

Takayuki Shibasaki, Hirotaka Tamura, Kouichi Kanda, Hisakatsu Yamaguchi, Junji Ogawa, Tadahiro Kuroda

Research output: Contribution to journalArticle

5 Citations (Scopus)

Abstract

This paper describes an 18-GHz coupled VCO array for low jitter and low phase deviation clock distribution. To reduce the skew, jitter and power consumption associated with clock distribution, the clock is generated by a one-dimensional VCO array in which the oscillating nodes of adjacent VCOs are directly connected with wires. The effects of the wire length and number of unit VCOs in the array are discussed. Both 4-unit and a 2-unit VCO arrays for delivering a clock signal to a 16:1 multiplexor were designed and fabricated in a 90-nm CMOS process. The frequency range of the 4-unit VCO array was 16 GHz to 18.5 GHz while each unit VCO consumed 2 mA.

Original languageEnglish
Pages (from-to)811-822
Number of pages12
JournalIEICE Transactions on Electronics
VolumeE90-C
Issue number4
DOIs
Publication statusPublished - 2007 Apr

Fingerprint

Variable frequency oscillators
Clocks
Jitter
Wire
Electric power utilization

Keywords

  • Clock distribution
  • High-speed I/O
  • Injection locking
  • Oscillators
  • Voltage-controlled oscillator

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Shibasaki, T., Tamura, H., Kanda, K., Yamaguchi, H., Ogawa, J., & Kuroda, T. (2007). 18-GHz clock distribution using a coupled VCO array. IEICE Transactions on Electronics, E90-C(4), 811-822. https://doi.org/10.1093/ietele/e90-c.4.811

18-GHz clock distribution using a coupled VCO array. / Shibasaki, Takayuki; Tamura, Hirotaka; Kanda, Kouichi; Yamaguchi, Hisakatsu; Ogawa, Junji; Kuroda, Tadahiro.

In: IEICE Transactions on Electronics, Vol. E90-C, No. 4, 04.2007, p. 811-822.

Research output: Contribution to journalArticle

Shibasaki, T, Tamura, H, Kanda, K, Yamaguchi, H, Ogawa, J & Kuroda, T 2007, '18-GHz clock distribution using a coupled VCO array', IEICE Transactions on Electronics, vol. E90-C, no. 4, pp. 811-822. https://doi.org/10.1093/ietele/e90-c.4.811
Shibasaki, Takayuki ; Tamura, Hirotaka ; Kanda, Kouichi ; Yamaguchi, Hisakatsu ; Ogawa, Junji ; Kuroda, Tadahiro. / 18-GHz clock distribution using a coupled VCO array. In: IEICE Transactions on Electronics. 2007 ; Vol. E90-C, No. 4. pp. 811-822.
@article{ecee21a54b5747d099d7007345b83bf6,
title = "18-GHz clock distribution using a coupled VCO array",
abstract = "This paper describes an 18-GHz coupled VCO array for low jitter and low phase deviation clock distribution. To reduce the skew, jitter and power consumption associated with clock distribution, the clock is generated by a one-dimensional VCO array in which the oscillating nodes of adjacent VCOs are directly connected with wires. The effects of the wire length and number of unit VCOs in the array are discussed. Both 4-unit and a 2-unit VCO arrays for delivering a clock signal to a 16:1 multiplexor were designed and fabricated in a 90-nm CMOS process. The frequency range of the 4-unit VCO array was 16 GHz to 18.5 GHz while each unit VCO consumed 2 mA.",
keywords = "Clock distribution, High-speed I/O, Injection locking, Oscillators, Voltage-controlled oscillator",
author = "Takayuki Shibasaki and Hirotaka Tamura and Kouichi Kanda and Hisakatsu Yamaguchi and Junji Ogawa and Tadahiro Kuroda",
year = "2007",
month = "4",
doi = "10.1093/ietele/e90-c.4.811",
language = "English",
volume = "E90-C",
pages = "811--822",
journal = "IEICE Transactions on Electronics",
issn = "0916-8524",
publisher = "Maruzen Co., Ltd/Maruzen Kabushikikaisha",
number = "4",

}

TY - JOUR

T1 - 18-GHz clock distribution using a coupled VCO array

AU - Shibasaki, Takayuki

AU - Tamura, Hirotaka

AU - Kanda, Kouichi

AU - Yamaguchi, Hisakatsu

AU - Ogawa, Junji

AU - Kuroda, Tadahiro

PY - 2007/4

Y1 - 2007/4

N2 - This paper describes an 18-GHz coupled VCO array for low jitter and low phase deviation clock distribution. To reduce the skew, jitter and power consumption associated with clock distribution, the clock is generated by a one-dimensional VCO array in which the oscillating nodes of adjacent VCOs are directly connected with wires. The effects of the wire length and number of unit VCOs in the array are discussed. Both 4-unit and a 2-unit VCO arrays for delivering a clock signal to a 16:1 multiplexor were designed and fabricated in a 90-nm CMOS process. The frequency range of the 4-unit VCO array was 16 GHz to 18.5 GHz while each unit VCO consumed 2 mA.

AB - This paper describes an 18-GHz coupled VCO array for low jitter and low phase deviation clock distribution. To reduce the skew, jitter and power consumption associated with clock distribution, the clock is generated by a one-dimensional VCO array in which the oscillating nodes of adjacent VCOs are directly connected with wires. The effects of the wire length and number of unit VCOs in the array are discussed. Both 4-unit and a 2-unit VCO arrays for delivering a clock signal to a 16:1 multiplexor were designed and fabricated in a 90-nm CMOS process. The frequency range of the 4-unit VCO array was 16 GHz to 18.5 GHz while each unit VCO consumed 2 mA.

KW - Clock distribution

KW - High-speed I/O

KW - Injection locking

KW - Oscillators

KW - Voltage-controlled oscillator

UR - http://www.scopus.com/inward/record.url?scp=34247092494&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=34247092494&partnerID=8YFLogxK

U2 - 10.1093/ietele/e90-c.4.811

DO - 10.1093/ietele/e90-c.4.811

M3 - Article

VL - E90-C

SP - 811

EP - 822

JO - IEICE Transactions on Electronics

JF - IEICE Transactions on Electronics

SN - 0916-8524

IS - 4

ER -