2 Gb/s 15 pJ/b/chip inductive-coupling programmable bus for NAND flash memory stacking

Mitsuko Saito, Yasufumi Sugimori, Yoshinori Kohama, Yoichi Yoshida, Noriyuki Miura, Hiroki Ishikuro, Takayasu Sakurai, Tadahiro Kuroda

Research output: Contribution to journalArticle

8 Citations (Scopus)

Abstract

An inductive-coupling programmable bus for NAND flash memory access in Solid State Drive (SSD) is presented. Compared to the conventional SSD, this wireless interface using relayed transmission reduces power consumption to 1/2, I/O circuitlayout area to 1/40, and achieves a data rate of 2 Gb/s in 0.18 m CMOS process. In addition, since this wireless interface enables one package to contain 64 chips, the number of packages is reduced to 1/8.

Original languageEnglish
Article number5357556
Pages (from-to)134-141
Number of pages8
JournalIEEE Journal of Solid-State Circuits
Volume45
Issue number1
DOIs
Publication statusPublished - 2010 Jan 1

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Keywords

  • Chip to chip
  • Inductive coupling
  • Memory stacking
  • SiP
  • Three-dimensional
  • Wireless interconnect

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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