2.2 Gbit/s Si bipolar 8 × 8 crosspoint switching LSI

Naoaki Yamanaka, Shiro Kikuchi, Masao Suzuki, Michihiro Hirata

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Abstract

A high-speed 8 × 8 space-division switching LSI has been developed for video and HDTV switching and broadcasting applications in the future B-ISDN. The LSI employs a new circuit design and super self-aligned process technology (SST-1A), and is switched successfully with a bit error rate of less than 10-9 at 2.5 Gbit/s using a 29-1 pseudorandom NRZ sequence. Pulse jitter has been limited to less than 70 ps at 2.2 Gbit/s by utilizing a small internal voltage swing (225 mV) employing a differential CML cell. The LSI has an ECL-compatible interface, -4.0 V and -2.0 V power supply voltages, and power dissipation of less than 997 mW. High-speed address control memories (ACMs) are integrated monolithically into the LSI, which can operate both synchronously and asynchronously.

Original languageEnglish
Pages (from-to)100-110
Number of pages11
JournalElectronics and Communications in Japan, Part II: Electronics (English translation of Denshi Tsushin Gakkai Ronbunshi)
Volume74
Issue number2
Publication statusPublished - 1991 Feb
Externally publishedYes

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ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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