A high-speed 8 × 8 space-division switching LSI has been developed for video and HDTV switching and broadcasting applications in the future B-ISDN. The LSI employs a new circuit design and super self-aligned process technology (SST-1A), and is switched successfully with a bit error rate of less than 10-9 at 2.5 Gbit/s using a 29-1 pseudorandom NRZ sequence. Pulse jitter has been limited to less than 70 ps at 2.2 Gbit/s by utilizing a small internal voltage swing (225 mV) employing a differential CML cell. The LSI has an ECL-compatible interface, -4.0 V and -2.0 V power supply voltages, and power dissipation of less than 997 mW. High-speed address control memories (ACMs) are integrated monolithically into the LSI, which can operate both synchronously and asynchronously.
|Number of pages||11|
|Journal||Electronics and Communications in Japan, Part II: Electronics (English translation of Denshi Tsushin Gakkai Ronbunshi)|
|Publication status||Published - 1991 Feb|
ASJC Scopus subject areas
- Electrical and Electronic Engineering