3-D system integration of processor and multi-stacked SRAMs using inductive-coupling link

Makoto Saen, Kenichi Osada, Yasuyuki Okuma, Kiichi Niitsu, Yasuhisa Shimazaki, Yasufumi Sugimori, Yoshinori Kohama, Kazutaka Kasuga, Itaru Nonomura, Naohiko Irie, Toshihiro Hattori, Atsushi Hasegawa, Tadahiro Kuroda

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21 Citations (Scopus)

Abstract

This paper describes a three-dimensional (3-D) system integration of a full-fledged processor chip and two memory chips using inductive coupling. To attain a 3-D communication link with a smaller area and lower power-consumption, shortening the link distance and preventing signal degradation due to unused inductors are important challenges. Therefore, we developed a new 3D-integrated wire-penetrated multi-layer structure for a shorter link distance and an open-skipped-inductor scheme for suppressing signal degradation. In addition, to avoid undefined-value propagation in stacking multi-memories using an inductive-coupling link, we proposed a memory-access-control scheme with a pinpoint-data-capture scheme. We demonstrate that three fabricated chips can be successfully AC-coupled using inductive coupling. The power and area efficiency of the link are 1 pJ/b and 0.15 mm2 /Gbps, respectively, which are the same as those of two-chip integration.

Original languageEnglish
Article number5437487
Pages (from-to)856-862
Number of pages7
JournalIEEE Journal of Solid-State Circuits
Volume45
Issue number4
DOIs
Publication statusPublished - 2010 Apr 1

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Keywords

  • Inductive coupling
  • Three-dimensional system integration

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Saen, M., Osada, K., Okuma, Y., Niitsu, K., Shimazaki, Y., Sugimori, Y., Kohama, Y., Kasuga, K., Nonomura, I., Irie, N., Hattori, T., Hasegawa, A., & Kuroda, T. (2010). 3-D system integration of processor and multi-stacked SRAMs using inductive-coupling link. IEEE Journal of Solid-State Circuits, 45(4), 856-862. [5437487]. https://doi.org/10.1109/JSSC.2010.2040310