3-D system integration of processor and multi-stacked SRAMs using inductive-coupling link

Makoto Saen, Kenichi Osada, Yasuyuki Okuma, Kiichi Niitsu, Yasuhisa Shimazaki, Yasufumi Sugimori, Yoshinori Kohama, Kazutaka Kasuga, Itaru Nonomura, Naohiko Irie, Toshihiro Hattori, Atsushi Hasegawa, Tadahiro Kuroda

Research output: Contribution to journalArticle

21 Citations (Scopus)

Abstract

This paper describes a three-dimensional (3-D) system integration of a full-fledged processor chip and two memory chips using inductive coupling. To attain a 3-D communication link with a smaller area and lower power-consumption, shortening the link distance and preventing signal degradation due to unused inductors are important challenges. Therefore, we developed a new 3D-integrated wire-penetrated multi-layer structure for a shorter link distance and an open-skipped-inductor scheme for suppressing signal degradation. In addition, to avoid undefined-value propagation in stacking multi-memories using an inductive-coupling link, we proposed a memory-access-control scheme with a pinpoint-data-capture scheme. We demonstrate that three fabricated chips can be successfully AC-coupled using inductive coupling. The power and area efficiency of the link are 1 pJ/b and 0.15 mm2 /Gbps, respectively, which are the same as those of two-chip integration.

Original languageEnglish
Article number5437487
Pages (from-to)856-862
Number of pages7
JournalIEEE Journal of Solid-State Circuits
Volume45
Issue number4
DOIs
Publication statusPublished - 2010 Apr

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Static random access storage
Data storage equipment
Degradation
Access control
Telecommunication links
Data acquisition
Electric power utilization
Wire

Keywords

  • Inductive coupling
  • Three-dimensional system integration

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

3-D system integration of processor and multi-stacked SRAMs using inductive-coupling link. / Saen, Makoto; Osada, Kenichi; Okuma, Yasuyuki; Niitsu, Kiichi; Shimazaki, Yasuhisa; Sugimori, Yasufumi; Kohama, Yoshinori; Kasuga, Kazutaka; Nonomura, Itaru; Irie, Naohiko; Hattori, Toshihiro; Hasegawa, Atsushi; Kuroda, Tadahiro.

In: IEEE Journal of Solid-State Circuits, Vol. 45, No. 4, 5437487, 04.2010, p. 856-862.

Research output: Contribution to journalArticle

Saen, M, Osada, K, Okuma, Y, Niitsu, K, Shimazaki, Y, Sugimori, Y, Kohama, Y, Kasuga, K, Nonomura, I, Irie, N, Hattori, T, Hasegawa, A & Kuroda, T 2010, '3-D system integration of processor and multi-stacked SRAMs using inductive-coupling link', IEEE Journal of Solid-State Circuits, vol. 45, no. 4, 5437487, pp. 856-862. https://doi.org/10.1109/JSSC.2010.2040310
Saen, Makoto ; Osada, Kenichi ; Okuma, Yasuyuki ; Niitsu, Kiichi ; Shimazaki, Yasuhisa ; Sugimori, Yasufumi ; Kohama, Yoshinori ; Kasuga, Kazutaka ; Nonomura, Itaru ; Irie, Naohiko ; Hattori, Toshihiro ; Hasegawa, Atsushi ; Kuroda, Tadahiro. / 3-D system integration of processor and multi-stacked SRAMs using inductive-coupling link. In: IEEE Journal of Solid-State Circuits. 2010 ; Vol. 45, No. 4. pp. 856-862.
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