3D clock distribution using vertically/horizontally-coupled resonators

Yasuhiro Take, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

Clock distribution with low skew, low jitter, and low power for high-performance microprocessors is a significant design challenge. Although traditional H-tree clock distribution circuits are widely used, the clock skew of such circuits is increased by the PVT variations associated with device scaling [1]. In recent years, there has thus been a growing interest in resonant clock distribution schemes for reduced clock skew. In particular, coupled ring oscillators with shorted outputs [2] can reduce skew and jitter without additional layout area compared to LC resonators [3]. The difference in phase and frequency of each oscillator (due to PVT variations) is equalized by the mutual connection between the oscillators. Power dissipation can also be reduced, as the enhanced variability tolerance may permit operation at lower voltages.

Original languageEnglish
Title of host publicationDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Pages258-259
Number of pages2
Volume56
DOIs
Publication statusPublished - 2013
Event2013 60th IEEE International Solid-State Circuits Conference, ISSCC 2013 - San Francisco, CA, United States
Duration: 2013 Feb 172013 Feb 21

Other

Other2013 60th IEEE International Solid-State Circuits Conference, ISSCC 2013
CountryUnited States
CitySan Francisco, CA
Period13/2/1713/2/21

Fingerprint

Clocks
Resonators
Jitter
Networks (circuits)
Microprocessor chips
Energy dissipation
Electric potential

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Take, Y., Miura, N., Ishikuro, H., & Kuroda, T. (2013). 3D clock distribution using vertically/horizontally-coupled resonators. In Digest of Technical Papers - IEEE International Solid-State Circuits Conference (Vol. 56, pp. 258-259). [6487725] https://doi.org/10.1109/ISSCC.2013.6487725

3D clock distribution using vertically/horizontally-coupled resonators. / Take, Yasuhiro; Miura, Noriyuki; Ishikuro, Hiroki; Kuroda, Tadahiro.

Digest of Technical Papers - IEEE International Solid-State Circuits Conference. Vol. 56 2013. p. 258-259 6487725.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Take, Y, Miura, N, Ishikuro, H & Kuroda, T 2013, 3D clock distribution using vertically/horizontally-coupled resonators. in Digest of Technical Papers - IEEE International Solid-State Circuits Conference. vol. 56, 6487725, pp. 258-259, 2013 60th IEEE International Solid-State Circuits Conference, ISSCC 2013, San Francisco, CA, United States, 13/2/17. https://doi.org/10.1109/ISSCC.2013.6487725
Take Y, Miura N, Ishikuro H, Kuroda T. 3D clock distribution using vertically/horizontally-coupled resonators. In Digest of Technical Papers - IEEE International Solid-State Circuits Conference. Vol. 56. 2013. p. 258-259. 6487725 https://doi.org/10.1109/ISSCC.2013.6487725
Take, Yasuhiro ; Miura, Noriyuki ; Ishikuro, Hiroki ; Kuroda, Tadahiro. / 3D clock distribution using vertically/horizontally-coupled resonators. Digest of Technical Papers - IEEE International Solid-State Circuits Conference. Vol. 56 2013. pp. 258-259
@inproceedings{fec77e81cd09409283359d9d918244a8,
title = "3D clock distribution using vertically/horizontally-coupled resonators",
abstract = "Clock distribution with low skew, low jitter, and low power for high-performance microprocessors is a significant design challenge. Although traditional H-tree clock distribution circuits are widely used, the clock skew of such circuits is increased by the PVT variations associated with device scaling [1]. In recent years, there has thus been a growing interest in resonant clock distribution schemes for reduced clock skew. In particular, coupled ring oscillators with shorted outputs [2] can reduce skew and jitter without additional layout area compared to LC resonators [3]. The difference in phase and frequency of each oscillator (due to PVT variations) is equalized by the mutual connection between the oscillators. Power dissipation can also be reduced, as the enhanced variability tolerance may permit operation at lower voltages.",
author = "Yasuhiro Take and Noriyuki Miura and Hiroki Ishikuro and Tadahiro Kuroda",
year = "2013",
doi = "10.1109/ISSCC.2013.6487725",
language = "English",
isbn = "9781467345132",
volume = "56",
pages = "258--259",
booktitle = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",

}

TY - GEN

T1 - 3D clock distribution using vertically/horizontally-coupled resonators

AU - Take, Yasuhiro

AU - Miura, Noriyuki

AU - Ishikuro, Hiroki

AU - Kuroda, Tadahiro

PY - 2013

Y1 - 2013

N2 - Clock distribution with low skew, low jitter, and low power for high-performance microprocessors is a significant design challenge. Although traditional H-tree clock distribution circuits are widely used, the clock skew of such circuits is increased by the PVT variations associated with device scaling [1]. In recent years, there has thus been a growing interest in resonant clock distribution schemes for reduced clock skew. In particular, coupled ring oscillators with shorted outputs [2] can reduce skew and jitter without additional layout area compared to LC resonators [3]. The difference in phase and frequency of each oscillator (due to PVT variations) is equalized by the mutual connection between the oscillators. Power dissipation can also be reduced, as the enhanced variability tolerance may permit operation at lower voltages.

AB - Clock distribution with low skew, low jitter, and low power for high-performance microprocessors is a significant design challenge. Although traditional H-tree clock distribution circuits are widely used, the clock skew of such circuits is increased by the PVT variations associated with device scaling [1]. In recent years, there has thus been a growing interest in resonant clock distribution schemes for reduced clock skew. In particular, coupled ring oscillators with shorted outputs [2] can reduce skew and jitter without additional layout area compared to LC resonators [3]. The difference in phase and frequency of each oscillator (due to PVT variations) is equalized by the mutual connection between the oscillators. Power dissipation can also be reduced, as the enhanced variability tolerance may permit operation at lower voltages.

UR - http://www.scopus.com/inward/record.url?scp=84876552989&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84876552989&partnerID=8YFLogxK

U2 - 10.1109/ISSCC.2013.6487725

DO - 10.1109/ISSCC.2013.6487725

M3 - Conference contribution

SN - 9781467345132

VL - 56

SP - 258

EP - 259

BT - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

ER -