3D layout of spidergon, flattened butterfly and dragonfly on a chip stack with inductive coupling through chip interface

Hiroshi Nakahara, Ryota Yasudo, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In most of recent Networks-on-Chip (NoCs), a simple 2D mesh structure has been adopted. However, the increasing latency caused by the large number of hops has become a problem especially in a large chip multiprocessor with increasing number of cores. Although using low ASPL networks which can reduce the hop count is a hopeful solution, a number of long wires often limits the operational frequency. Hence, we propose 3D layout of three networks: Spidergon, Flattened Butterfly, and Dragonfly on a chip stack with wireless inductive coupling through chip interface (TCI). By making the use of TCI properties, including flexible stacking and chip pass-Through data transfer, the maximum length of wires is much reduced. A large system which uses many chips can easily be implemented without degrading operational frequency.

Original languageEnglish
Title of host publicationProceedings - 14th International Symposium on Pervasive Systems, Algorithms and Networks, I-SPAN 2017, 11th International Conference on Frontier of Computer Science and Technology, FCST 2017 and 3rd International Symposium of Creative Computing, ISCC 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages52-59
Number of pages8
Volume2017-November
ISBN (Electronic)9781538608401
DOIs
Publication statusPublished - 2017 Nov 27
Event14th International Symposium on Pervasive Systems, Algorithms and Networks, I-SPAN 2017, 11th International Conference on Frontier of Computer Science and Technology, FCST 2017 and 3rd International Symposium of Creative Computing, ISCC 2017 - Exeter, Devon, United Kingdom
Duration: 2017 Jun 212017 Jun 23

Other

Other14th International Symposium on Pervasive Systems, Algorithms and Networks, I-SPAN 2017, 11th International Conference on Frontier of Computer Science and Technology, FCST 2017 and 3rd International Symposium of Creative Computing, ISCC 2017
CountryUnited Kingdom
CityExeter, Devon
Period17/6/2117/6/23

Fingerprint

Wire
Data transfer
Network-on-chip

ASJC Scopus subject areas

  • Industrial and Manufacturing Engineering
  • Control and Systems Engineering
  • Computer Science(all)
  • Electrical and Electronic Engineering

Cite this

Nakahara, H., Yasudo, R., Matsutani, H., Amano, H., & Koibuchi, M. (2017). 3D layout of spidergon, flattened butterfly and dragonfly on a chip stack with inductive coupling through chip interface. In Proceedings - 14th International Symposium on Pervasive Systems, Algorithms and Networks, I-SPAN 2017, 11th International Conference on Frontier of Computer Science and Technology, FCST 2017 and 3rd International Symposium of Creative Computing, ISCC 2017 (Vol. 2017-November, pp. 52-59). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISPAN-FCST-ISCC.2017.82

3D layout of spidergon, flattened butterfly and dragonfly on a chip stack with inductive coupling through chip interface. / Nakahara, Hiroshi; Yasudo, Ryota; Matsutani, Hiroki; Amano, Hideharu; Koibuchi, Michihiro.

Proceedings - 14th International Symposium on Pervasive Systems, Algorithms and Networks, I-SPAN 2017, 11th International Conference on Frontier of Computer Science and Technology, FCST 2017 and 3rd International Symposium of Creative Computing, ISCC 2017. Vol. 2017-November Institute of Electrical and Electronics Engineers Inc., 2017. p. 52-59.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Nakahara, H, Yasudo, R, Matsutani, H, Amano, H & Koibuchi, M 2017, 3D layout of spidergon, flattened butterfly and dragonfly on a chip stack with inductive coupling through chip interface. in Proceedings - 14th International Symposium on Pervasive Systems, Algorithms and Networks, I-SPAN 2017, 11th International Conference on Frontier of Computer Science and Technology, FCST 2017 and 3rd International Symposium of Creative Computing, ISCC 2017. vol. 2017-November, Institute of Electrical and Electronics Engineers Inc., pp. 52-59, 14th International Symposium on Pervasive Systems, Algorithms and Networks, I-SPAN 2017, 11th International Conference on Frontier of Computer Science and Technology, FCST 2017 and 3rd International Symposium of Creative Computing, ISCC 2017, Exeter, Devon, United Kingdom, 17/6/21. https://doi.org/10.1109/ISPAN-FCST-ISCC.2017.82
Nakahara H, Yasudo R, Matsutani H, Amano H, Koibuchi M. 3D layout of spidergon, flattened butterfly and dragonfly on a chip stack with inductive coupling through chip interface. In Proceedings - 14th International Symposium on Pervasive Systems, Algorithms and Networks, I-SPAN 2017, 11th International Conference on Frontier of Computer Science and Technology, FCST 2017 and 3rd International Symposium of Creative Computing, ISCC 2017. Vol. 2017-November. Institute of Electrical and Electronics Engineers Inc. 2017. p. 52-59 https://doi.org/10.1109/ISPAN-FCST-ISCC.2017.82
Nakahara, Hiroshi ; Yasudo, Ryota ; Matsutani, Hiroki ; Amano, Hideharu ; Koibuchi, Michihiro. / 3D layout of spidergon, flattened butterfly and dragonfly on a chip stack with inductive coupling through chip interface. Proceedings - 14th International Symposium on Pervasive Systems, Algorithms and Networks, I-SPAN 2017, 11th International Conference on Frontier of Computer Science and Technology, FCST 2017 and 3rd International Symposium of Creative Computing, ISCC 2017. Vol. 2017-November Institute of Electrical and Electronics Engineers Inc., 2017. pp. 52-59
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