3D System integration of processor and multi-stacked SRAMs by using inductive-coupling links

Kenichi Osada, Makoto Saen, Yasuyuki Okuma, Kiichi Niitsu, Yasuhisa Shimazaki, Yasufumi Sugimori, Yoshinori Kohama, Kazutaka Kasuga, Itaru Nonomura, Naohiko Irie, Toshihiro Hattori, Atsushi Hasegawa, Tadahiro Kuroda

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    16 Citations (Scopus)


    This paper describes a three-dimensional (3D) system integration of a fully functional processor chip and two memory chips by using inductive coupling. To attain a shorter link distance for a smaller area and lower power consumption, a new 3D-integrated wire-penetrated multi-layer structure is developed. In addition, to prevent signal degradation due to unused inductors, an "open-skipped-inductor scheme" is proposed. We present the first demonstration that three fabricated chips are successfully AC-coupled by the inductive coupling. The power and area efficiency of the link are 1 pJ/b and 0.15 mm2/Gbps, respectively, which are the same as those of two-chip integration.

    Original languageEnglish
    Title of host publication2009 Symposium on VLSI Circuits
    Number of pages2
    Publication statusPublished - 2009 Nov 18
    Event2009 Symposium on VLSI Circuits - Kyoto, Japan
    Duration: 2009 Jun 162009 Jun 18

    Publication series

    NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers


    Other2009 Symposium on VLSI Circuits


    • 3D system integration
    • Inductive coupling link
    • Memory
    • Processor

    ASJC Scopus subject areas

    • Electronic, Optical and Magnetic Materials
    • Electrical and Electronic Engineering


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