3D System integration of processor and multi-stacked SRAMs by using inductive-coupling links

Kenichi Osada; Makoto Saen; Yasuyuki Okuma; Kiichi Niitsu; Yasuhisa Shimazaki; Yasufumi Sugimori; Yoshinori Kohama; Kazutaka Kasuga; Itaru Nonomura; Naohiko Irie; Toshihiro Hattori; Atsushi Hasegawa; Tadahiro Kuroda

3D System integration of processor and multi-stacked SRAMs by using inductive-coupling links

Kenichi Osada, Makoto Saen, Yasuyuki Okuma, Kiichi Niitsu, Yasuhisa Shimazaki, Yasufumi Sugimori, Yoshinori Kohama, Kazutaka Kasuga, Itaru Nonomura, Naohiko Irie, Toshihiro Hattori, Atsushi Hasegawa, Tadahiro Kuroda

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

16 Citations (Scopus)

Abstract

This paper describes a three-dimensional (3D) system integration of a fully functional processor chip and two memory chips by using inductive coupling. To attain a shorter link distance for a smaller area and lower power consumption, a new 3D-integrated wire-penetrated multi-layer structure is developed. In addition, to prevent signal degradation due to unused inductors, an "open-skipped-inductor scheme" is proposed. We present the first demonstration that three fabricated chips are successfully AC-coupled by the inductive coupling. The power and area efficiency of the link are 1 pJ/b and 0.15 mm2/Gbps, respectively, which are the same as those of two-chip integration.

Original language	English
Title of host publication	2009 Symposium on VLSI Circuits
Pages	256-257
Number of pages	2
Publication status	Published - 2009 Nov 18
Event	2009 Symposium on VLSI Circuits - Kyoto, Japan Duration: 2009 Jun 16 → 2009 Jun 18

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Other

Other	2009 Symposium on VLSI Circuits
Country/Territory	Japan
City	Kyoto
Period	09/6/16 → 09/6/18

Keywords

3D system integration
Inductive coupling link
Memory
Processor

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Cite this

Osada, K., Saen, M., Okuma, Y., Niitsu, K., Shimazaki, Y., Sugimori, Y., Kohama, Y., Kasuga, K., Nonomura, I., Irie, N., Hattori, T., Hasegawa, A., & Kuroda, T. (2009). 3D System integration of processor and multi-stacked SRAMs by using inductive-coupling links. In 2009 Symposium on VLSI Circuits (pp. 256-257). [5205351] (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

Osada, K, Saen, M, Okuma, Y, Niitsu, K, Shimazaki, Y, Sugimori, Y, Kohama, Y, Kasuga, K, Nonomura, I, Irie, N, Hattori, T, Hasegawa, A & Kuroda, T 2009, 3D System integration of processor and multi-stacked SRAMs by using inductive-coupling links. in 2009 Symposium on VLSI Circuits., 5205351, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, pp. 256-257, 2009 Symposium on VLSI Circuits, Kyoto, Japan, 09/6/16.

@inproceedings{b57c865df09c4177b4cf545bc28c2e69,

title = "3D System integration of processor and multi-stacked SRAMs by using inductive-coupling links",

abstract = "This paper describes a three-dimensional (3D) system integration of a fully functional processor chip and two memory chips by using inductive coupling. To attain a shorter link distance for a smaller area and lower power consumption, a new 3D-integrated wire-penetrated multi-layer structure is developed. In addition, to prevent signal degradation due to unused inductors, an {"}open-skipped-inductor scheme{"} is proposed. We present the first demonstration that three fabricated chips are successfully AC-coupled by the inductive coupling. The power and area efficiency of the link are 1 pJ/b and 0.15 mm2/Gbps, respectively, which are the same as those of two-chip integration.",

keywords = "3D system integration, Inductive coupling link, Memory, Processor",

author = "Kenichi Osada and Makoto Saen and Yasuyuki Okuma and Kiichi Niitsu and Yasuhisa Shimazaki and Yasufumi Sugimori and Yoshinori Kohama and Kazutaka Kasuga and Itaru Nonomura and Naohiko Irie and Toshihiro Hattori and Atsushi Hasegawa and Tadahiro Kuroda",

year = "2009",

month = nov,

day = "18",

language = "English",

isbn = "9784863480018",

series = "IEEE Symposium on VLSI Circuits, Digest of Technical Papers",

pages = "256--257",

booktitle = "2009 Symposium on VLSI Circuits",

note = "2009 Symposium on VLSI Circuits ; Conference date: 16-06-2009 Through 18-06-2009",

}

TY - GEN

T1 - 3D System integration of processor and multi-stacked SRAMs by using inductive-coupling links

AU - Osada, Kenichi

AU - Saen, Makoto

AU - Okuma, Yasuyuki

AU - Niitsu, Kiichi

AU - Shimazaki, Yasuhisa

AU - Sugimori, Yasufumi

AU - Kohama, Yoshinori

AU - Kasuga, Kazutaka

AU - Nonomura, Itaru

AU - Irie, Naohiko

AU - Hattori, Toshihiro

AU - Hasegawa, Atsushi

AU - Kuroda, Tadahiro

PY - 2009/11/18

Y1 - 2009/11/18

N2 - This paper describes a three-dimensional (3D) system integration of a fully functional processor chip and two memory chips by using inductive coupling. To attain a shorter link distance for a smaller area and lower power consumption, a new 3D-integrated wire-penetrated multi-layer structure is developed. In addition, to prevent signal degradation due to unused inductors, an "open-skipped-inductor scheme" is proposed. We present the first demonstration that three fabricated chips are successfully AC-coupled by the inductive coupling. The power and area efficiency of the link are 1 pJ/b and 0.15 mm2/Gbps, respectively, which are the same as those of two-chip integration.

AB - This paper describes a three-dimensional (3D) system integration of a fully functional processor chip and two memory chips by using inductive coupling. To attain a shorter link distance for a smaller area and lower power consumption, a new 3D-integrated wire-penetrated multi-layer structure is developed. In addition, to prevent signal degradation due to unused inductors, an "open-skipped-inductor scheme" is proposed. We present the first demonstration that three fabricated chips are successfully AC-coupled by the inductive coupling. The power and area efficiency of the link are 1 pJ/b and 0.15 mm2/Gbps, respectively, which are the same as those of two-chip integration.

KW - 3D system integration

KW - Inductive coupling link

KW - Memory

KW - Processor

UR - http://www.scopus.com/inward/record.url?scp=70449376846&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=70449376846&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:70449376846

SN - 9784863480018

T3 - IEEE Symposium on VLSI Circuits, Digest of Technical Papers

SP - 256

EP - 257

BT - 2009 Symposium on VLSI Circuits

T2 - 2009 Symposium on VLSI Circuits

Y2 - 16 June 2009 through 18 June 2009

ER -

3D System integration of processor and multi-stacked SRAMs by using inductive-coupling links

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Keywords

ASJC Scopus subject areas

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