47% power reduction and 91% area reduction in inductive-coupling programmable bus for NAND flash memory stacking

Mitsuko Saito; Yoichi Yoshida; Noriyuki Miura; Hiroki Ishikuro; Tadahiro Kuroda

doi:10.1109/TCSI.2010.2071670

47% power reduction and 91% area reduction in inductive-coupling programmable bus for NAND flash memory stacking

Mitsuko Saito, Yoichi Yoshida, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda

Department of Electronics and Electrical Engineering

Research output: Contribution to journal › Article › peer-review

11 Citations (Scopus)

Abstract

This paper presents a power reduction scheme and an area reduction scheme in inductive-coupling programmable bus for NAND flash memory stacking. A channel arrangement scheme using three coils enables random access for memory read and memory write. Transmit power is reduced by 47% compared to a previous design with shields. A coil layout style, herein noted as XY coil, allows for the coils to interleave with logic interconnections, resulting in area reduction of 91% relative to at the expense of only 17% transmit power increase. Relayed data transmission at 1.6 Gb/s and BER < 10^-12 is achieved.

Original language	English
Article number	5582165
Pages (from-to)	2269-2278
Number of pages	10
Journal	IEEE Transactions on Circuits and Systems I: Regular Papers
Volume	57
Issue number	9
DOIs	https://doi.org/10.1109/TCSI.2010.2071670
Publication status	Published - 2010

Keywords

Inductive coupling
NAND flash
memory stacking
solid-state drive (SSD)
three-dimensional
wireless interconnect

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/TCSI.2010.2071670

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title = "47% power reduction and 91% area reduction in inductive-coupling programmable bus for NAND flash memory stacking",

abstract = "This paper presents a power reduction scheme and an area reduction scheme in inductive-coupling programmable bus for NAND flash memory stacking. A channel arrangement scheme using three coils enables random access for memory read and memory write. Transmit power is reduced by 47% compared to a previous design with shields. A coil layout style, herein noted as XY coil, allows for the coils to interleave with logic interconnections, resulting in area reduction of 91% relative to at the expense of only 17% transmit power increase. Relayed data transmission at 1.6 Gb/s and BER < 10-12 is achieved.",

keywords = "Inductive coupling, NAND flash, memory stacking, solid-state drive (SSD), three-dimensional, wireless interconnect",

author = "Mitsuko Saito and Yoichi Yoshida and Noriyuki Miura and Hiroki Ishikuro and Tadahiro Kuroda",

note = "Funding Information: Manuscript received March 30, 2010; revised June 18, 2010; accepted July 14, 2010. Date of publication September 23, 2010; date of current version October 01, 2010. This work is supported by CREST/JST. This paper was recommended by Associate Editor J. Rogers. Funding Information: This work is supported by CREST/JST.",

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AU - Saito, Mitsuko

AU - Yoshida, Yoichi

AU - Miura, Noriyuki

AU - Ishikuro, Hiroki

AU - Kuroda, Tadahiro

N1 - Funding Information: Manuscript received March 30, 2010; revised June 18, 2010; accepted July 14, 2010. Date of publication September 23, 2010; date of current version October 01, 2010. This work is supported by CREST/JST. This paper was recommended by Associate Editor J. Rogers. Funding Information: This work is supported by CREST/JST.

PY - 2010

Y1 - 2010

N2 - This paper presents a power reduction scheme and an area reduction scheme in inductive-coupling programmable bus for NAND flash memory stacking. A channel arrangement scheme using three coils enables random access for memory read and memory write. Transmit power is reduced by 47% compared to a previous design with shields. A coil layout style, herein noted as XY coil, allows for the coils to interleave with logic interconnections, resulting in area reduction of 91% relative to at the expense of only 17% transmit power increase. Relayed data transmission at 1.6 Gb/s and BER < 10-12 is achieved.

AB - This paper presents a power reduction scheme and an area reduction scheme in inductive-coupling programmable bus for NAND flash memory stacking. A channel arrangement scheme using three coils enables random access for memory read and memory write. Transmit power is reduced by 47% compared to a previous design with shields. A coil layout style, herein noted as XY coil, allows for the coils to interleave with logic interconnections, resulting in area reduction of 91% relative to at the expense of only 17% transmit power increase. Relayed data transmission at 1.6 Gb/s and BER < 10-12 is achieved.

KW - Inductive coupling

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KW - solid-state drive (SSD)

KW - three-dimensional

KW - wireless interconnect

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47% power reduction and 91% area reduction in inductive-coupling programmable bus for NAND flash memory stacking

Abstract

Keywords

ASJC Scopus subject areas

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