47% power reduction and 91% area reduction in inductive-coupling programmable bus for NAND flash memory stacking

Mitsuko Saito, Yoichi Yoshida, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda

    Research output: Contribution to journalArticlepeer-review

    8 Citations (Scopus)

    Abstract

    This paper presents a power reduction scheme and an area reduction scheme in inductive-coupling programmable bus for NAND flash memory stacking. A channel arrangement scheme using three coils enables random access for memory read and memory write. Transmit power is reduced by 47% compared to a previous design with shields. A coil layout style, herein noted as XY coil, allows for the coils to interleave with logic interconnections, resulting in area reduction of 91% relative to at the expense of only 17% transmit power increase. Relayed data transmission at 1.6 Gb/s and BER < 10-12 is achieved.

    Original languageEnglish
    Article number5582165
    Pages (from-to)2269-2278
    Number of pages10
    JournalIEEE Transactions on Circuits and Systems I: Regular Papers
    Volume57
    Issue number9
    DOIs
    Publication statusPublished - 2010 Sep 24

    Keywords

    • Inductive coupling
    • NAND flash
    • memory stacking
    • solid-state drive (SSD)
    • three-dimensional
    • wireless interconnect

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering

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