47% power reduction and 91% area reduction in inductive-coupling programmable bus for NAND flash memory stacking

Mitsuko Saito, Yasufumi Sugimori, Yoshinori Kohama, Yoichi Yoshida, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

An inductive-coupling programmable bus is developed for NAND flash memory access in Solid State Drive (SSD). A channel arrangement scheme using 3 coils enables random access for memory read and memory write. Transmission power is reduced by 47% compared to a previous design with 2 coils and a shield [1]. A coil layout style, namely XY coil, allows the coils covered by logic interconnections, resulting in area reduction by 91%. Relayed data transmission at 1.6Gb/s and BER<10-12 is achieved.

Original languageEnglish
Title of host publicationProceedings of the Custom Integrated Circuits Conference
Pages449-452
Number of pages4
DOIs
Publication statusPublished - 2009
Event2009 IEEE Custom Integrated Circuits Conference, CICC '09 - San Jose, CA, United States
Duration: 2009 Sep 132009 Sep 16

Other

Other2009 IEEE Custom Integrated Circuits Conference, CICC '09
CountryUnited States
CitySan Jose, CA
Period09/9/1309/9/16

Fingerprint

Flash memory
Data storage equipment
Power transmission
Data communication systems

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Saito, M., Sugimori, Y., Kohama, Y., Yoshida, Y., Miura, N., Ishikuro, H., & Kuroda, T. (2009). 47% power reduction and 91% area reduction in inductive-coupling programmable bus for NAND flash memory stacking. In Proceedings of the Custom Integrated Circuits Conference (pp. 449-452). [5280819] https://doi.org/10.1109/CICC.2009.5280819

47% power reduction and 91% area reduction in inductive-coupling programmable bus for NAND flash memory stacking. / Saito, Mitsuko; Sugimori, Yasufumi; Kohama, Yoshinori; Yoshida, Yoichi; Miura, Noriyuki; Ishikuro, Hiroki; Kuroda, Tadahiro.

Proceedings of the Custom Integrated Circuits Conference. 2009. p. 449-452 5280819.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Saito, M, Sugimori, Y, Kohama, Y, Yoshida, Y, Miura, N, Ishikuro, H & Kuroda, T 2009, 47% power reduction and 91% area reduction in inductive-coupling programmable bus for NAND flash memory stacking. in Proceedings of the Custom Integrated Circuits Conference., 5280819, pp. 449-452, 2009 IEEE Custom Integrated Circuits Conference, CICC '09, San Jose, CA, United States, 09/9/13. https://doi.org/10.1109/CICC.2009.5280819
Saito M, Sugimori Y, Kohama Y, Yoshida Y, Miura N, Ishikuro H et al. 47% power reduction and 91% area reduction in inductive-coupling programmable bus for NAND flash memory stacking. In Proceedings of the Custom Integrated Circuits Conference. 2009. p. 449-452. 5280819 https://doi.org/10.1109/CICC.2009.5280819
Saito, Mitsuko ; Sugimori, Yasufumi ; Kohama, Yoshinori ; Yoshida, Yoichi ; Miura, Noriyuki ; Ishikuro, Hiroki ; Kuroda, Tadahiro. / 47% power reduction and 91% area reduction in inductive-coupling programmable bus for NAND flash memory stacking. Proceedings of the Custom Integrated Circuits Conference. 2009. pp. 449-452
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