47% power reduction and 91% area reduction in inductive-coupling programmable bus for NAND flash memory stacking

Mitsuko Saito; Yasufumi Sugimori; Yoshinori Kohama; Yoichi Yoshida; Noriyuki Miura; Hiroki Ishikuro; Tadahiro Kuroda

doi:10.1109/CICC.2009.5280819

47% power reduction and 91% area reduction in inductive-coupling programmable bus for NAND flash memory stacking

Mitsuko Saito, Yasufumi Sugimori, Yoshinori Kohama, Yoichi Yoshida, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

8 Citations (Scopus)

Abstract

An inductive-coupling programmable bus is developed for NAND flash memory access in Solid State Drive (SSD). A channel arrangement scheme using 3 coils enables random access for memory read and memory write. Transmission power is reduced by 47% compared to a previous design with 2 coils and a shield [1]. A coil layout style, namely XY coil, allows the coils covered by logic interconnections, resulting in area reduction by 91%. Relayed data transmission at 1.6Gb/s and BER<10^-12 is achieved.

Original language	English
Title of host publication	2009 IEEE Custom Integrated Circuits Conference, CICC '09
Pages	449-452
Number of pages	4
DOIs	https://doi.org/10.1109/CICC.2009.5280819
Publication status	Published - 2009 Dec 1
Event	2009 IEEE Custom Integrated Circuits Conference, CICC '09 - San Jose, CA, United States Duration: 2009 Sept 13 → 2009 Sept 16

Publication series

Name	Proceedings of the Custom Integrated Circuits Conference
ISSN (Print)	0886-5930

Other

Other	2009 IEEE Custom Integrated Circuits Conference, CICC '09
Country/Territory	United States
City	San Jose, CA
Period	09/9/13 → 09/9/16

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/CICC.2009.5280819

Cite this

Saito, M., Sugimori, Y., Kohama, Y., Yoshida, Y., Miura, N., Ishikuro, H., & Kuroda, T. (2009). 47% power reduction and 91% area reduction in inductive-coupling programmable bus for NAND flash memory stacking. In 2009 IEEE Custom Integrated Circuits Conference, CICC '09 (pp. 449-452). [5280819] (Proceedings of the Custom Integrated Circuits Conference). https://doi.org/10.1109/CICC.2009.5280819

47% power reduction and 91% area reduction in inductive-coupling programmable bus for NAND flash memory stacking. / Saito, Mitsuko; Sugimori, Yasufumi; Kohama, Yoshinori et al.

2009 IEEE Custom Integrated Circuits Conference, CICC '09. 2009. p. 449-452 5280819 (Proceedings of the Custom Integrated Circuits Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Saito, M, Sugimori, Y, Kohama, Y, Yoshida, Y, Miura, N, Ishikuro, H & Kuroda, T 2009, 47% power reduction and 91% area reduction in inductive-coupling programmable bus for NAND flash memory stacking. in 2009 IEEE Custom Integrated Circuits Conference, CICC '09., 5280819, Proceedings of the Custom Integrated Circuits Conference, pp. 449-452, 2009 IEEE Custom Integrated Circuits Conference, CICC '09, San Jose, CA, United States, 09/9/13. https://doi.org/10.1109/CICC.2009.5280819

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47% power reduction and 91% area reduction in inductive-coupling programmable bus for NAND flash memory stacking

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