50% active-power saving without speed degradation using standby power reduction (SPR) circuit

Katsuhiro Seta, Hiroyuki Hara, Tadahiro Kuroda, Masakazu Kakumu, Takayasu Sakurai

Research output: Chapter in Book/Report/Conference proceedingConference contribution

49 Citations (Scopus)

Abstract

To understand circuit delay and power dissipation dependence on power supply voltage (VDD) and threshold voltage (VTH) of MOSFETs, a typical logic circuit is investigated. Fanout is chosen to be 5 which corresponds to the statistical average of gate load in ASICs. If VTH is reduced to 0.3 V, VDD can be decreased down to 2 V while maintaining the speed at VTH = 0.7 V and VDD = 3 V which is the typical operation condition for high-speed LSIs. The active power dissipation, in this case, is reduced by more than 50%.

Original languageEnglish
Title of host publicationDigest of Technical Papers - IEEE International Solid-State Circuits Conference
PublisherIEEE
Pages318-319
Number of pages2
Volume38
Publication statusPublished - 1995 Feb
Externally publishedYes
EventProceedings of the 1995 IEEE International Solid-State Circuits Conference - San Francisco, CA, USA
Duration: 1995 Feb 151995 Feb 17

Other

OtherProceedings of the 1995 IEEE International Solid-State Circuits Conference
CitySan Francisco, CA, USA
Period95/2/1595/2/17

Fingerprint

Threshold voltage
Degradation
Networks (circuits)
Energy dissipation
Delay circuits
Logic circuits
Application specific integrated circuits
Electric potential

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Seta, K., Hara, H., Kuroda, T., Kakumu, M., & Sakurai, T. (1995). 50% active-power saving without speed degradation using standby power reduction (SPR) circuit. In Digest of Technical Papers - IEEE International Solid-State Circuits Conference (Vol. 38, pp. 318-319). IEEE.

50% active-power saving without speed degradation using standby power reduction (SPR) circuit. / Seta, Katsuhiro; Hara, Hiroyuki; Kuroda, Tadahiro; Kakumu, Masakazu; Sakurai, Takayasu.

Digest of Technical Papers - IEEE International Solid-State Circuits Conference. Vol. 38 IEEE, 1995. p. 318-319.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Seta, K, Hara, H, Kuroda, T, Kakumu, M & Sakurai, T 1995, 50% active-power saving without speed degradation using standby power reduction (SPR) circuit. in Digest of Technical Papers - IEEE International Solid-State Circuits Conference. vol. 38, IEEE, pp. 318-319, Proceedings of the 1995 IEEE International Solid-State Circuits Conference, San Francisco, CA, USA, 95/2/15.
Seta K, Hara H, Kuroda T, Kakumu M, Sakurai T. 50% active-power saving without speed degradation using standby power reduction (SPR) circuit. In Digest of Technical Papers - IEEE International Solid-State Circuits Conference. Vol. 38. IEEE. 1995. p. 318-319
Seta, Katsuhiro ; Hara, Hiroyuki ; Kuroda, Tadahiro ; Kakumu, Masakazu ; Sakurai, Takayasu. / 50% active-power saving without speed degradation using standby power reduction (SPR) circuit. Digest of Technical Papers - IEEE International Solid-State Circuits Conference. Vol. 38 IEEE, 1995. pp. 318-319
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