### Abstract

To understand circuit delay and power dissipation dependence on power supply voltage (V_{DD}) and threshold voltage (V_{TH}) of MOSFETs, a typical logic circuit is investigated. Fanout is chosen to be 5 which corresponds to the statistical average of gate load in ASICs. If V_{TH} is reduced to 0.3 V, V_{DD} can be decreased down to 2 V while maintaining the speed at V_{TH} = 0.7 V and V_{DD} = 3 V which is the typical operation condition for high-speed LSIs. The active power dissipation, in this case, is reduced by more than 50%.

Original language | English |
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Pages (from-to) | 318-319 |

Number of pages | 2 |

Journal | Digest of Technical Papers - IEEE International Solid-State Circuits Conference |

Volume | 38 |

Publication status | Published - 1995 Feb 1 |

Externally published | Yes |

Event | Proceedings of the 1995 IEEE International Solid-State Circuits Conference - San Francisco, CA, USA Duration: 1995 Feb 15 → 1995 Feb 17 |

### ASJC Scopus subject areas

- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering

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## Cite this

Seta, K., Hara, H., Kuroda, T., Kakumu, M., & Sakurai, T. (1995). 50% active-power saving without speed degradation using standby power reduction (SPR) circuit.

*Digest of Technical Papers - IEEE International Solid-State Circuits Conference*,*38*, 318-319.