### Abstract

To understand circuit delay and power dissipation dependence on power supply voltage (V_{DD}) and threshold voltage (V_{TH}) of MOSFETs, a typical logic circuit is investigated. Fanout is chosen to be 5 which corresponds to the statistical average of gate load in ASICs. If V_{TH} is reduced to 0.3 V, V_{DD} can be decreased down to 2 V while maintaining the speed at V_{TH} = 0.7 V and V_{DD} = 3 V which is the typical operation condition for high-speed LSIs. The active power dissipation, in this case, is reduced by more than 50%.

Original language | English |
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Title of host publication | Digest of Technical Papers - IEEE International Solid-State Circuits Conference |

Publisher | IEEE |

Pages | 318-319 |

Number of pages | 2 |

Volume | 38 |

Publication status | Published - 1995 Feb |

Externally published | Yes |

Event | Proceedings of the 1995 IEEE International Solid-State Circuits Conference - San Francisco, CA, USA Duration: 1995 Feb 15 → 1995 Feb 17 |

### Other

Other | Proceedings of the 1995 IEEE International Solid-State Circuits Conference |
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City | San Francisco, CA, USA |

Period | 95/2/15 → 95/2/17 |

### Fingerprint

### ASJC Scopus subject areas

- Hardware and Architecture
- Electrical and Electronic Engineering

### Cite this

*Digest of Technical Papers - IEEE International Solid-State Circuits Conference*(Vol. 38, pp. 318-319). IEEE.

**50% active-power saving without speed degradation using standby power reduction (SPR) circuit.** / Seta, Katsuhiro; Hara, Hiroyuki; Kuroda, Tadahiro; Kakumu, Masakazu; Sakurai, Takayasu.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

*Digest of Technical Papers - IEEE International Solid-State Circuits Conference.*vol. 38, IEEE, pp. 318-319, Proceedings of the 1995 IEEE International Solid-State Circuits Conference, San Francisco, CA, USA, 95/2/15.

}

TY - GEN

T1 - 50% active-power saving without speed degradation using standby power reduction (SPR) circuit

AU - Seta, Katsuhiro

AU - Hara, Hiroyuki

AU - Kuroda, Tadahiro

AU - Kakumu, Masakazu

AU - Sakurai, Takayasu

PY - 1995/2

Y1 - 1995/2

N2 - To understand circuit delay and power dissipation dependence on power supply voltage (VDD) and threshold voltage (VTH) of MOSFETs, a typical logic circuit is investigated. Fanout is chosen to be 5 which corresponds to the statistical average of gate load in ASICs. If VTH is reduced to 0.3 V, VDD can be decreased down to 2 V while maintaining the speed at VTH = 0.7 V and VDD = 3 V which is the typical operation condition for high-speed LSIs. The active power dissipation, in this case, is reduced by more than 50%.

AB - To understand circuit delay and power dissipation dependence on power supply voltage (VDD) and threshold voltage (VTH) of MOSFETs, a typical logic circuit is investigated. Fanout is chosen to be 5 which corresponds to the statistical average of gate load in ASICs. If VTH is reduced to 0.3 V, VDD can be decreased down to 2 V while maintaining the speed at VTH = 0.7 V and VDD = 3 V which is the typical operation condition for high-speed LSIs. The active power dissipation, in this case, is reduced by more than 50%.

UR - http://www.scopus.com/inward/record.url?scp=0029253931&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0029253931&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0029253931

VL - 38

SP - 318

EP - 319

BT - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

PB - IEEE

ER -