50% active-power saving without speed degradation using standby power reduction (SPR) circuit

Katsuhiro Seta, Hiroyuki Hara, Tadahiro Kuroda, Masakazu Kakumu, Takayasu Sakurai

Research output: Contribution to journalConference article

49 Citations (Scopus)


To understand circuit delay and power dissipation dependence on power supply voltage (VDD) and threshold voltage (VTH) of MOSFETs, a typical logic circuit is investigated. Fanout is chosen to be 5 which corresponds to the statistical average of gate load in ASICs. If VTH is reduced to 0.3 V, VDD can be decreased down to 2 V while maintaining the speed at VTH = 0.7 V and VDD = 3 V which is the typical operation condition for high-speed LSIs. The active power dissipation, in this case, is reduced by more than 50%.

Original languageEnglish
Pages (from-to)318-319
Number of pages2
JournalDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Publication statusPublished - 1995 Feb 1
Externally publishedYes
EventProceedings of the 1995 IEEE International Solid-State Circuits Conference - San Francisco, CA, USA
Duration: 1995 Feb 151995 Feb 17


ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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