50% Active-power saving without speed degradation using standby power reduction (spr) circuit

Katsuhiro Seta, Hiroyuki Hara, Tadahiro Kuroda, Masakazu Kakumu, Takayasu Sakurai

Research output: Chapter in Book/Report/Conference proceedingChapter

Original languageEnglish
Title of host publicationLow-Power CMOS Design
PublisherJohn Wiley and Sons Inc.
Pages95-96
Number of pages2
ISBN (Electronic)9780470545058
ISBN (Print)9780780334298
DOIs
Publication statusPublished - 1998 Jan 1
Externally publishedYes

ASJC Scopus subject areas

  • Engineering(all)
  • Computer Science(all)
  • Energy(all)

Cite this

Seta, K., Hara, H., Kuroda, T., Kakumu, M., & Sakurai, T. (1998). 50% Active-power saving without speed degradation using standby power reduction (spr) circuit. In Low-Power CMOS Design (pp. 95-96). John Wiley and Sons Inc.. https://doi.org/10.1109/9780470545058.sect3