51k-gate low power ECL gate array family with metal-compiled and embedded SRAM

D. Gray, D. Beeson, G. Daves, D. Hutchings, P. Thai, T. S. Wong, T. Kuroda, M. Nakamura, M. Noda

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

A family of 80ps, 1mW/gate series-gated ECL gate arrays of up to 51k-gate density is described. The family supports both metal-compiled SRAM with a TAA of 2.0ns. Raw core densities of 1125 gates/mm2 are achieved using a true ocean-of-cells, channel-less architecture. The arrays are fabricated using the ASSET-1 (All Spacer-Separated Element Transistor) 2-poly, 3-layer metal process with a conservative 1.2um emitter lithography.

Original languageEnglish
Title of host publicationProceedings of the Custom Integrated Circuits Conference
PublisherPubl by IEEE
Pages23.4.1-23.4.4
ISBN (Print)0780308263
Publication statusPublished - 1993 Jan 1
Externally publishedYes
EventProceedings of the IEEE 1993 Custom Integrated Circuits Conference - San Diego, CA, USA
Duration: 1993 May 91993 May 12

Publication series

NameProceedings of the Custom Integrated Circuits Conference
ISSN (Print)0886-5930

Other

OtherProceedings of the IEEE 1993 Custom Integrated Circuits Conference
CitySan Diego, CA, USA
Period93/5/993/5/12

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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  • Cite this

    Gray, D., Beeson, D., Daves, G., Hutchings, D., Thai, P., Wong, T. S., Kuroda, T., Nakamura, M., & Noda, M. (1993). 51k-gate low power ECL gate array family with metal-compiled and embedded SRAM. In Proceedings of the Custom Integrated Circuits Conference (pp. 23.4.1-23.4.4). (Proceedings of the Custom Integrated Circuits Conference). Publ by IEEE.