60% power reduction in inductive-coupling inter-chip link by current-sensing technique

Kiichi Niitsu, Noriyuki Miura, Mari Inoue, Yoshihiro Nakagawa, Masamoto Tago, Masayuki Mizuno, Hiroki Ishikuro, Tadahiro Kuroda

Research output: Contribution to journalArticle

9 Citations (Scopus)

Abstract

The demand for low-power and high-speed chip-to-chip communication between stacked chips in a system in a package (SiP) is increasing day by day. We have proposed and investigated a novel current-sensing technique in an inductive-coupling interchip link. Our current-sensing technique reduces total power dissipation by 60% compared with the conventional voltage-sensing technique without sacrificing either data rate (1 Gbit/s per channel) or bit error rate (<10-12). Additionally, the voltage-sensing technique and the current-sensing technique are compared from the viewpoint of circuit topology and the immunity to device mismatch. From a circuit simulation, the current-sensing technique was shown to have higher immunity to device mismatch and can reduce the transmitter power compared with voltage-sensing technique. We have reached a conclusion that the current-sensing technique is very effective for low-power operation in an inductive-coupling inter-chip link.

Original languageEnglish
Pages (from-to)2215-2219
Number of pages5
JournalJapanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers
Volume46
Issue number4 B
DOIs
Publication statusPublished - 2007 Apr 24

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chips
Electric potential
Electric network topology
Circuit simulation
Bit error rate
Transmitters
Energy dissipation
immunity
electric potential
Communication
bit error rate
transmitters
topology
dissipation
communication
high speed
simulation

Keywords

  • Current-sensing technique
  • Inductive coupling
  • Inter-chip communication
  • Stacked chip
  • Wireless

ASJC Scopus subject areas

  • Physics and Astronomy (miscellaneous)

Cite this

60% power reduction in inductive-coupling inter-chip link by current-sensing technique. / Niitsu, Kiichi; Miura, Noriyuki; Inoue, Mari; Nakagawa, Yoshihiro; Tago, Masamoto; Mizuno, Masayuki; Ishikuro, Hiroki; Kuroda, Tadahiro.

In: Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers, Vol. 46, No. 4 B, 24.04.2007, p. 2215-2219.

Research output: Contribution to journalArticle

Niitsu, Kiichi ; Miura, Noriyuki ; Inoue, Mari ; Nakagawa, Yoshihiro ; Tago, Masamoto ; Mizuno, Masayuki ; Ishikuro, Hiroki ; Kuroda, Tadahiro. / 60% power reduction in inductive-coupling inter-chip link by current-sensing technique. In: Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers. 2007 ; Vol. 46, No. 4 B. pp. 2215-2219.
@article{a452dfe2685940bc87edb55aba1bedb7,
title = "60{\%} power reduction in inductive-coupling inter-chip link by current-sensing technique",
abstract = "The demand for low-power and high-speed chip-to-chip communication between stacked chips in a system in a package (SiP) is increasing day by day. We have proposed and investigated a novel current-sensing technique in an inductive-coupling interchip link. Our current-sensing technique reduces total power dissipation by 60{\%} compared with the conventional voltage-sensing technique without sacrificing either data rate (1 Gbit/s per channel) or bit error rate (<10-12). Additionally, the voltage-sensing technique and the current-sensing technique are compared from the viewpoint of circuit topology and the immunity to device mismatch. From a circuit simulation, the current-sensing technique was shown to have higher immunity to device mismatch and can reduce the transmitter power compared with voltage-sensing technique. We have reached a conclusion that the current-sensing technique is very effective for low-power operation in an inductive-coupling inter-chip link.",
keywords = "Current-sensing technique, Inductive coupling, Inter-chip communication, Stacked chip, Wireless",
author = "Kiichi Niitsu and Noriyuki Miura and Mari Inoue and Yoshihiro Nakagawa and Masamoto Tago and Masayuki Mizuno and Hiroki Ishikuro and Tadahiro Kuroda",
year = "2007",
month = "4",
day = "24",
doi = "10.1143/JJAP.46.2215",
language = "English",
volume = "46",
pages = "2215--2219",
journal = "Japanese Journal of Applied Physics, Part 1: Regular Papers & Short Notes",
issn = "0021-4922",
publisher = "Japan Society of Applied Physics",
number = "4 B",

}

TY - JOUR

T1 - 60% power reduction in inductive-coupling inter-chip link by current-sensing technique

AU - Niitsu, Kiichi

AU - Miura, Noriyuki

AU - Inoue, Mari

AU - Nakagawa, Yoshihiro

AU - Tago, Masamoto

AU - Mizuno, Masayuki

AU - Ishikuro, Hiroki

AU - Kuroda, Tadahiro

PY - 2007/4/24

Y1 - 2007/4/24

N2 - The demand for low-power and high-speed chip-to-chip communication between stacked chips in a system in a package (SiP) is increasing day by day. We have proposed and investigated a novel current-sensing technique in an inductive-coupling interchip link. Our current-sensing technique reduces total power dissipation by 60% compared with the conventional voltage-sensing technique without sacrificing either data rate (1 Gbit/s per channel) or bit error rate (<10-12). Additionally, the voltage-sensing technique and the current-sensing technique are compared from the viewpoint of circuit topology and the immunity to device mismatch. From a circuit simulation, the current-sensing technique was shown to have higher immunity to device mismatch and can reduce the transmitter power compared with voltage-sensing technique. We have reached a conclusion that the current-sensing technique is very effective for low-power operation in an inductive-coupling inter-chip link.

AB - The demand for low-power and high-speed chip-to-chip communication between stacked chips in a system in a package (SiP) is increasing day by day. We have proposed and investigated a novel current-sensing technique in an inductive-coupling interchip link. Our current-sensing technique reduces total power dissipation by 60% compared with the conventional voltage-sensing technique without sacrificing either data rate (1 Gbit/s per channel) or bit error rate (<10-12). Additionally, the voltage-sensing technique and the current-sensing technique are compared from the viewpoint of circuit topology and the immunity to device mismatch. From a circuit simulation, the current-sensing technique was shown to have higher immunity to device mismatch and can reduce the transmitter power compared with voltage-sensing technique. We have reached a conclusion that the current-sensing technique is very effective for low-power operation in an inductive-coupling inter-chip link.

KW - Current-sensing technique

KW - Inductive coupling

KW - Inter-chip communication

KW - Stacked chip

KW - Wireless

UR - http://www.scopus.com/inward/record.url?scp=34547880467&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=34547880467&partnerID=8YFLogxK

U2 - 10.1143/JJAP.46.2215

DO - 10.1143/JJAP.46.2215

M3 - Article

AN - SCOPUS:34547880467

VL - 46

SP - 2215

EP - 2219

JO - Japanese Journal of Applied Physics, Part 1: Regular Papers & Short Notes

JF - Japanese Journal of Applied Physics, Part 1: Regular Papers & Short Notes

SN - 0021-4922

IS - 4 B

ER -