60% power reduction in inductive-coupling inter-chip link by current-sensing technique

Kiichi Niitsu, Noriyuki Miura, Mari Inoue, Yoshihiro Nakagawa, Masamoto Tago, Masayuki Mizuno, Hiroki Ishikuro, Tadahiro Kuroda

    Research output: Contribution to journalArticlepeer-review

    9 Citations (Scopus)


    The demand for low-power and high-speed chip-to-chip communication between stacked chips in a system in a package (SiP) is increasing day by day. We have proposed and investigated a novel current-sensing technique in an inductive-coupling interchip link. Our current-sensing technique reduces total power dissipation by 60% compared with the conventional voltage-sensing technique without sacrificing either data rate (1 Gbit/s per channel) or bit error rate (<10-12). Additionally, the voltage-sensing technique and the current-sensing technique are compared from the viewpoint of circuit topology and the immunity to device mismatch. From a circuit simulation, the current-sensing technique was shown to have higher immunity to device mismatch and can reduce the transmitter power compared with voltage-sensing technique. We have reached a conclusion that the current-sensing technique is very effective for low-power operation in an inductive-coupling inter-chip link.

    Original languageEnglish
    Pages (from-to)2215-2219
    Number of pages5
    JournalJapanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers
    Issue number4 B
    Publication statusPublished - 2007 Apr 24


    • Current-sensing technique
    • Inductive coupling
    • Inter-chip communication
    • Stacked chip
    • Wireless

    ASJC Scopus subject areas

    • Engineering(all)
    • Physics and Astronomy(all)

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