7-bit 0.8-1.2GS/s Dynamic Architecture and Frequency Scaling subrange ADC with binary-search/flash Live Configuring Technique

Kentaro Yoshioka, Ryo Saito, Takumi Danjo, Sanroku Tsukamoto, Hiroki Ishikuro

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

Subrange ADC with Dynamic Architecture and Frequency Scaling(DAFS) is presented, which has exponential power scaling against frequency with high-speed operation of over 1GS/s. We propose Live Configuring Technique(LCT) to adaptively configure the sub-ADC operation between binary-search and flash every clock cycle, reflecting the conversion delay. The power consumption is cut down significantly and retains high-speed operation. The prototype ADC fabricated in 65nm CMOS operates up to 1228MS/s and achieves an SNDR 36.2dB at nyquist. DAFS is active between 800-1200MS/s and when compared with the frequency power scaling with DAFS disabled, the peak power consumption cut down is 30%. Peak FoM of 85fJ/conv. was obtained at 820MS/s, which is nearly a 2x improvement compared with reported subrange ADCs.

Original languageEnglish
Title of host publicationIEEE Symposium on VLSI Circuits, Digest of Technical Papers
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Print)9781479933273
DOIs
Publication statusPublished - 2014
Event28th IEEE Symposium on VLSI Circuits, VLSIC 2014 - Honolulu, HI, United States
Duration: 2014 Jun 102014 Jun 13

Other

Other28th IEEE Symposium on VLSI Circuits, VLSIC 2014
CountryUnited States
CityHonolulu, HI
Period14/6/1014/6/13

Fingerprint

Electric power utilization
Clocks

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Yoshioka, K., Saito, R., Danjo, T., Tsukamoto, S., & Ishikuro, H. (2014). 7-bit 0.8-1.2GS/s Dynamic Architecture and Frequency Scaling subrange ADC with binary-search/flash Live Configuring Technique. In IEEE Symposium on VLSI Circuits, Digest of Technical Papers [6858374] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSIC.2014.6858374

7-bit 0.8-1.2GS/s Dynamic Architecture and Frequency Scaling subrange ADC with binary-search/flash Live Configuring Technique. / Yoshioka, Kentaro; Saito, Ryo; Danjo, Takumi; Tsukamoto, Sanroku; Ishikuro, Hiroki.

IEEE Symposium on VLSI Circuits, Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2014. 6858374.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Yoshioka, K, Saito, R, Danjo, T, Tsukamoto, S & Ishikuro, H 2014, 7-bit 0.8-1.2GS/s Dynamic Architecture and Frequency Scaling subrange ADC with binary-search/flash Live Configuring Technique. in IEEE Symposium on VLSI Circuits, Digest of Technical Papers., 6858374, Institute of Electrical and Electronics Engineers Inc., 28th IEEE Symposium on VLSI Circuits, VLSIC 2014, Honolulu, HI, United States, 14/6/10. https://doi.org/10.1109/VLSIC.2014.6858374
Yoshioka K, Saito R, Danjo T, Tsukamoto S, Ishikuro H. 7-bit 0.8-1.2GS/s Dynamic Architecture and Frequency Scaling subrange ADC with binary-search/flash Live Configuring Technique. In IEEE Symposium on VLSI Circuits, Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc. 2014. 6858374 https://doi.org/10.1109/VLSIC.2014.6858374
Yoshioka, Kentaro ; Saito, Ryo ; Danjo, Takumi ; Tsukamoto, Sanroku ; Ishikuro, Hiroki. / 7-bit 0.8-1.2GS/s Dynamic Architecture and Frequency Scaling subrange ADC with binary-search/flash Live Configuring Technique. IEEE Symposium on VLSI Circuits, Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2014.
@inproceedings{f360d2cf3b0248b9a91d8b8f0db75141,
title = "7-bit 0.8-1.2GS/s Dynamic Architecture and Frequency Scaling subrange ADC with binary-search/flash Live Configuring Technique",
abstract = "Subrange ADC with Dynamic Architecture and Frequency Scaling(DAFS) is presented, which has exponential power scaling against frequency with high-speed operation of over 1GS/s. We propose Live Configuring Technique(LCT) to adaptively configure the sub-ADC operation between binary-search and flash every clock cycle, reflecting the conversion delay. The power consumption is cut down significantly and retains high-speed operation. The prototype ADC fabricated in 65nm CMOS operates up to 1228MS/s and achieves an SNDR 36.2dB at nyquist. DAFS is active between 800-1200MS/s and when compared with the frequency power scaling with DAFS disabled, the peak power consumption cut down is 30{\%}. Peak FoM of 85fJ/conv. was obtained at 820MS/s, which is nearly a 2x improvement compared with reported subrange ADCs.",
author = "Kentaro Yoshioka and Ryo Saito and Takumi Danjo and Sanroku Tsukamoto and Hiroki Ishikuro",
year = "2014",
doi = "10.1109/VLSIC.2014.6858374",
language = "English",
isbn = "9781479933273",
booktitle = "IEEE Symposium on VLSI Circuits, Digest of Technical Papers",
publisher = "Institute of Electrical and Electronics Engineers Inc.",

}

TY - GEN

T1 - 7-bit 0.8-1.2GS/s Dynamic Architecture and Frequency Scaling subrange ADC with binary-search/flash Live Configuring Technique

AU - Yoshioka, Kentaro

AU - Saito, Ryo

AU - Danjo, Takumi

AU - Tsukamoto, Sanroku

AU - Ishikuro, Hiroki

PY - 2014

Y1 - 2014

N2 - Subrange ADC with Dynamic Architecture and Frequency Scaling(DAFS) is presented, which has exponential power scaling against frequency with high-speed operation of over 1GS/s. We propose Live Configuring Technique(LCT) to adaptively configure the sub-ADC operation between binary-search and flash every clock cycle, reflecting the conversion delay. The power consumption is cut down significantly and retains high-speed operation. The prototype ADC fabricated in 65nm CMOS operates up to 1228MS/s and achieves an SNDR 36.2dB at nyquist. DAFS is active between 800-1200MS/s and when compared with the frequency power scaling with DAFS disabled, the peak power consumption cut down is 30%. Peak FoM of 85fJ/conv. was obtained at 820MS/s, which is nearly a 2x improvement compared with reported subrange ADCs.

AB - Subrange ADC with Dynamic Architecture and Frequency Scaling(DAFS) is presented, which has exponential power scaling against frequency with high-speed operation of over 1GS/s. We propose Live Configuring Technique(LCT) to adaptively configure the sub-ADC operation between binary-search and flash every clock cycle, reflecting the conversion delay. The power consumption is cut down significantly and retains high-speed operation. The prototype ADC fabricated in 65nm CMOS operates up to 1228MS/s and achieves an SNDR 36.2dB at nyquist. DAFS is active between 800-1200MS/s and when compared with the frequency power scaling with DAFS disabled, the peak power consumption cut down is 30%. Peak FoM of 85fJ/conv. was obtained at 820MS/s, which is nearly a 2x improvement compared with reported subrange ADCs.

UR - http://www.scopus.com/inward/record.url?scp=84905659274&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84905659274&partnerID=8YFLogxK

U2 - 10.1109/VLSIC.2014.6858374

DO - 10.1109/VLSIC.2014.6858374

M3 - Conference contribution

AN - SCOPUS:84905659274

SN - 9781479933273

BT - IEEE Symposium on VLSI Circuits, Digest of Technical Papers

PB - Institute of Electrical and Electronics Engineers Inc.

ER -