A 0.0058mm2 7.0 ENOB 24MS/s 17fJ/conv. threshold configuring SAR ADC with source voltage shifting and interpolation technique

Kentaro Yoshioka, Akira Shikata, Ryota Sekimoto, Tadahiro Kuroda, Hiroki Ishikuro

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Citations (Scopus)

Abstract

An extremely low power and area efficient threshold configuring ADC (TC-ADC) is proposed. The threshold configuring comparator (TCC) performs a binary search and only 1b-DAC is required. 5b conversion is carried out by TCC with source voltage shifting technique. Additional 2b resolution is achieved by the proposed threshold interpolation (TI) technique with only 15% power overhead. Prototype ADC in 40nm CMOS occupies a core area of only 0.0038mm 2 and when calibration circuit included, 0.0058 mm2. With a supply voltage of 0.7V, the ADC achieves 7.0 ENOB with 24MS/s. Peak FoM of 9.8fJ/conv. is obtained at 0.5V supply, which is over 15x improvement compared with conventional TC-ADC.

Original languageEnglish
Title of host publicationIEEE Symposium on VLSI Circuits, Digest of Technical Papers
Publication statusPublished - 2013
Event2013 Symposium on VLSI Circuits, VLSIC 2013 - Kyoto, Japan
Duration: 2013 Jun 122013 Jun 14

Other

Other2013 Symposium on VLSI Circuits, VLSIC 2013
CountryJapan
CityKyoto
Period13/6/1213/6/14

Fingerprint

Interpolation
Electric potential
Calibration
Networks (circuits)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Yoshioka, K., Shikata, A., Sekimoto, R., Kuroda, T., & Ishikuro, H. (2013). A 0.0058mm2 7.0 ENOB 24MS/s 17fJ/conv. threshold configuring SAR ADC with source voltage shifting and interpolation technique. In IEEE Symposium on VLSI Circuits, Digest of Technical Papers [6578689]

A 0.0058mm2 7.0 ENOB 24MS/s 17fJ/conv. threshold configuring SAR ADC with source voltage shifting and interpolation technique. / Yoshioka, Kentaro; Shikata, Akira; Sekimoto, Ryota; Kuroda, Tadahiro; Ishikuro, Hiroki.

IEEE Symposium on VLSI Circuits, Digest of Technical Papers. 2013. 6578689.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Yoshioka, K, Shikata, A, Sekimoto, R, Kuroda, T & Ishikuro, H 2013, A 0.0058mm2 7.0 ENOB 24MS/s 17fJ/conv. threshold configuring SAR ADC with source voltage shifting and interpolation technique. in IEEE Symposium on VLSI Circuits, Digest of Technical Papers., 6578689, 2013 Symposium on VLSI Circuits, VLSIC 2013, Kyoto, Japan, 13/6/12.
Yoshioka K, Shikata A, Sekimoto R, Kuroda T, Ishikuro H. A 0.0058mm2 7.0 ENOB 24MS/s 17fJ/conv. threshold configuring SAR ADC with source voltage shifting and interpolation technique. In IEEE Symposium on VLSI Circuits, Digest of Technical Papers. 2013. 6578689
Yoshioka, Kentaro ; Shikata, Akira ; Sekimoto, Ryota ; Kuroda, Tadahiro ; Ishikuro, Hiroki. / A 0.0058mm2 7.0 ENOB 24MS/s 17fJ/conv. threshold configuring SAR ADC with source voltage shifting and interpolation technique. IEEE Symposium on VLSI Circuits, Digest of Technical Papers. 2013.
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