A 0.11μm CMOS clocked comparator for high-speed serial communications

Yusuke Okaniwa, Hirotaka Tamura, Masaya Kibune, Daisuke Yamazaki, TszShing Cheung, Junji Ogawa, Nestoras Tzartzanis, William W. Walker, Tadahiro Kuroda

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Citations (Scopus)

Abstract

A differential comparator targeted at receiving 40 Gb/s signals and operating off a single 1.2V supply was designed and fabricated in 0.11 μm CMOS. It comprises a front-end sampler and a regenerative stage with a clocked buffer to achieve a narrow aperture time and a high toggle rate. The regenerative stage output buffer employs an impedance modulation technique based on switching of feedback gain to reduce the reset time while keeping the effective gain high. We confirmed comparator operation with BER less than 10-12 up to 32 Gb/s at a toggle rate of 8 GHz.

Original languageEnglish
Title of host publicationIEEE Symposium on VLSI Circuits, Digest of Technical Papers
Pages198-201
Number of pages4
EditionCIRCUITS SYMP.
Publication statusPublished - 2004
Event2004 Symposium on VLSI Circuits, Digest of Technical Papers, 2004 VLSI - Honolulu, HI, United States
Duration: 2004 Jun 172004 Jun 19

Other

Other2004 Symposium on VLSI Circuits, Digest of Technical Papers, 2004 VLSI
CountryUnited States
CityHonolulu, HI
Period04/6/1704/6/19

Fingerprint

Communication
Modulation
Feedback

Keywords

  • CMOS
  • Comparator
  • Regenerative latch

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Okaniwa, Y., Tamura, H., Kibune, M., Yamazaki, D., Cheung, T., Ogawa, J., ... Kuroda, T. (2004). A 0.11μm CMOS clocked comparator for high-speed serial communications. In IEEE Symposium on VLSI Circuits, Digest of Technical Papers (CIRCUITS SYMP. ed., pp. 198-201)

A 0.11μm CMOS clocked comparator for high-speed serial communications. / Okaniwa, Yusuke; Tamura, Hirotaka; Kibune, Masaya; Yamazaki, Daisuke; Cheung, TszShing; Ogawa, Junji; Tzartzanis, Nestoras; Walker, William W.; Kuroda, Tadahiro.

IEEE Symposium on VLSI Circuits, Digest of Technical Papers. CIRCUITS SYMP. ed. 2004. p. 198-201.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Okaniwa, Y, Tamura, H, Kibune, M, Yamazaki, D, Cheung, T, Ogawa, J, Tzartzanis, N, Walker, WW & Kuroda, T 2004, A 0.11μm CMOS clocked comparator for high-speed serial communications. in IEEE Symposium on VLSI Circuits, Digest of Technical Papers. CIRCUITS SYMP. edn, pp. 198-201, 2004 Symposium on VLSI Circuits, Digest of Technical Papers, 2004 VLSI, Honolulu, HI, United States, 04/6/17.
Okaniwa Y, Tamura H, Kibune M, Yamazaki D, Cheung T, Ogawa J et al. A 0.11μm CMOS clocked comparator for high-speed serial communications. In IEEE Symposium on VLSI Circuits, Digest of Technical Papers. CIRCUITS SYMP. ed. 2004. p. 198-201
Okaniwa, Yusuke ; Tamura, Hirotaka ; Kibune, Masaya ; Yamazaki, Daisuke ; Cheung, TszShing ; Ogawa, Junji ; Tzartzanis, Nestoras ; Walker, William W. ; Kuroda, Tadahiro. / A 0.11μm CMOS clocked comparator for high-speed serial communications. IEEE Symposium on VLSI Circuits, Digest of Technical Papers. CIRCUITS SYMP. ed. 2004. pp. 198-201
@inproceedings{5a0b10f9258448d789f2fdf880b554e1,
title = "A 0.11μm CMOS clocked comparator for high-speed serial communications",
abstract = "A differential comparator targeted at receiving 40 Gb/s signals and operating off a single 1.2V supply was designed and fabricated in 0.11 μm CMOS. It comprises a front-end sampler and a regenerative stage with a clocked buffer to achieve a narrow aperture time and a high toggle rate. The regenerative stage output buffer employs an impedance modulation technique based on switching of feedback gain to reduce the reset time while keeping the effective gain high. We confirmed comparator operation with BER less than 10-12 up to 32 Gb/s at a toggle rate of 8 GHz.",
keywords = "CMOS, Comparator, Regenerative latch",
author = "Yusuke Okaniwa and Hirotaka Tamura and Masaya Kibune and Daisuke Yamazaki and TszShing Cheung and Junji Ogawa and Nestoras Tzartzanis and Walker, {William W.} and Tadahiro Kuroda",
year = "2004",
language = "English",
pages = "198--201",
booktitle = "IEEE Symposium on VLSI Circuits, Digest of Technical Papers",
edition = "CIRCUITS SYMP.",

}

TY - GEN

T1 - A 0.11μm CMOS clocked comparator for high-speed serial communications

AU - Okaniwa, Yusuke

AU - Tamura, Hirotaka

AU - Kibune, Masaya

AU - Yamazaki, Daisuke

AU - Cheung, TszShing

AU - Ogawa, Junji

AU - Tzartzanis, Nestoras

AU - Walker, William W.

AU - Kuroda, Tadahiro

PY - 2004

Y1 - 2004

N2 - A differential comparator targeted at receiving 40 Gb/s signals and operating off a single 1.2V supply was designed and fabricated in 0.11 μm CMOS. It comprises a front-end sampler and a regenerative stage with a clocked buffer to achieve a narrow aperture time and a high toggle rate. The regenerative stage output buffer employs an impedance modulation technique based on switching of feedback gain to reduce the reset time while keeping the effective gain high. We confirmed comparator operation with BER less than 10-12 up to 32 Gb/s at a toggle rate of 8 GHz.

AB - A differential comparator targeted at receiving 40 Gb/s signals and operating off a single 1.2V supply was designed and fabricated in 0.11 μm CMOS. It comprises a front-end sampler and a regenerative stage with a clocked buffer to achieve a narrow aperture time and a high toggle rate. The regenerative stage output buffer employs an impedance modulation technique based on switching of feedback gain to reduce the reset time while keeping the effective gain high. We confirmed comparator operation with BER less than 10-12 up to 32 Gb/s at a toggle rate of 8 GHz.

KW - CMOS

KW - Comparator

KW - Regenerative latch

UR - http://www.scopus.com/inward/record.url?scp=4544327301&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=4544327301&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:4544327301

SP - 198

EP - 201

BT - IEEE Symposium on VLSI Circuits, Digest of Technical Papers

ER -