A 0.11μm CMOS clocked comparator for high-speed serial communications

Yusuke Okaniwa, Hirotaka Tamura, Masaya Kibune, Daisuke Yamazaki, Tsz Shing Cheung, Junji Ogawa, Nestoras Tzartzanis, William W. Walker, Tadahiro Kuroda

Research output: Contribution to conferencePaper

10 Citations (Scopus)

Abstract

A differential comparator targeted at receiving 40 Gb/s signals and operating off a single 1.2V supply was designed and fabricated in 0.11 μm CMOS. It comprises a front-end sampler and a regenerative stage with a clocked buffer to achieve a narrow aperture time and a high toggle rate. The regenerative stage output buffer employs an impedance modulation technique based on switching of feedback gain to reduce the reset time while keeping the effective gain high. We confirmed comparator operation with BER less than 10-12 up to 32 Gb/s at a toggle rate of 8 GHz.

Original languageEnglish
Pages198-201
Number of pages4
Publication statusPublished - 2004 Sep 29
Event2004 Symposium on VLSI Circuits, Digest of Technical Papers, 2004 VLSI - Honolulu, HI, United States
Duration: 2004 Jun 172004 Jun 19

Other

Other2004 Symposium on VLSI Circuits, Digest of Technical Papers, 2004 VLSI
CountryUnited States
CityHonolulu, HI
Period04/6/1704/6/19

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Keywords

  • CMOS
  • Comparator
  • Regenerative latch

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Okaniwa, Y., Tamura, H., Kibune, M., Yamazaki, D., Cheung, T. S., Ogawa, J., Tzartzanis, N., Walker, W. W., & Kuroda, T. (2004). A 0.11μm CMOS clocked comparator for high-speed serial communications. 198-201. Paper presented at 2004 Symposium on VLSI Circuits, Digest of Technical Papers, 2004 VLSI, Honolulu, HI, United States.