A 0.35-0.8V 8b 0.5-35MS/s 2bit/step extremely-low power SAR ADC

Kentaro Yoshioka, Akira Shikata, Ryota Sekimoto, Tadahiro Kuroda, Hiroki Ishikuro

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Abstract

    An extremely low-voltage operating high speed and low power 2bit/step asynchronous SAR ADC is presented. Wide range dynamic threshold configuring comparator is proposed to enable power and area efficient 2bit/step operation. By configuring the comparator threshold by simple Vcm biased current sources, the ADC holds immunity against 10% power supply variation. The prototype ADC fabricated in 40nm CMOS achieved 44.3 dB SNDR with 6.14 MS/s at a single supply voltage of 0.5 V. The ADC achieved a peak FoM of 5.9fJ/conv-step at 0.4V and operates down to 0.35V.

    Original languageEnglish
    Title of host publication2013 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013
    Pages111-112
    Number of pages2
    DOIs
    Publication statusPublished - 2013 May 20
    Event2013 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013 - Yokohama, Japan
    Duration: 2013 Jan 222013 Jan 25

    Publication series

    NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

    Other

    Other2013 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013
    CountryJapan
    CityYokohama
    Period13/1/2213/1/25

    ASJC Scopus subject areas

    • Computer Science Applications
    • Computer Graphics and Computer-Aided Design
    • Electrical and Electronic Engineering

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  • Cite this

    Yoshioka, K., Shikata, A., Sekimoto, R., Kuroda, T., & Ishikuro, H. (2013). A 0.35-0.8V 8b 0.5-35MS/s 2bit/step extremely-low power SAR ADC. In 2013 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013 (pp. 111-112). [6509581] (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). https://doi.org/10.1109/ASPDAC.2013.6509581