A 0.35-0.8V 8b 0.5-35MS/s 2bit/step extremely-low power SAR ADC

Kentaro Yoshioka, Akira Shikata, Ryota Sekimoto, Tadahiro Kuroda, Hiroki Ishikuro

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

An extremely low-voltage operating high speed and low power 2bit/step asynchronous SAR ADC is presented. Wide range dynamic threshold configuring comparator is proposed to enable power and area efficient 2bit/step operation. By configuring the comparator threshold by simple Vcm biased current sources, the ADC holds immunity against 10% power supply variation. The prototype ADC fabricated in 40nm CMOS achieved 44.3 dB SNDR with 6.14 MS/s at a single supply voltage of 0.5 V. The ADC achieved a peak FoM of 5.9fJ/conv-step at 0.4V and operates down to 0.35V.

Original languageEnglish
Title of host publicationProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Pages111-112
Number of pages2
DOIs
Publication statusPublished - 2013
Event2013 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013 - Yokohama, Japan
Duration: 2013 Jan 222013 Jan 25

Other

Other2013 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013
CountryJapan
CityYokohama
Period13/1/2213/1/25

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ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design

Cite this

Yoshioka, K., Shikata, A., Sekimoto, R., Kuroda, T., & Ishikuro, H. (2013). A 0.35-0.8V 8b 0.5-35MS/s 2bit/step extremely-low power SAR ADC. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC (pp. 111-112). [6509581] https://doi.org/10.1109/ASPDAC.2013.6509581

A 0.35-0.8V 8b 0.5-35MS/s 2bit/step extremely-low power SAR ADC. / Yoshioka, Kentaro; Shikata, Akira; Sekimoto, Ryota; Kuroda, Tadahiro; Ishikuro, Hiroki.

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. 2013. p. 111-112 6509581.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Yoshioka, K, Shikata, A, Sekimoto, R, Kuroda, T & Ishikuro, H 2013, A 0.35-0.8V 8b 0.5-35MS/s 2bit/step extremely-low power SAR ADC. in Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC., 6509581, pp. 111-112, 2013 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013, Yokohama, Japan, 13/1/22. https://doi.org/10.1109/ASPDAC.2013.6509581
Yoshioka K, Shikata A, Sekimoto R, Kuroda T, Ishikuro H. A 0.35-0.8V 8b 0.5-35MS/s 2bit/step extremely-low power SAR ADC. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. 2013. p. 111-112. 6509581 https://doi.org/10.1109/ASPDAC.2013.6509581
Yoshioka, Kentaro ; Shikata, Akira ; Sekimoto, Ryota ; Kuroda, Tadahiro ; Ishikuro, Hiroki. / A 0.35-0.8V 8b 0.5-35MS/s 2bit/step extremely-low power SAR ADC. Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. 2013. pp. 111-112
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